EE 3714 Digital Devices Home page, Robert Reese, FALL 2001


Lectures     Lab Page

Policy/Syllabus

This is the Policy/Syllabus for this course.

EE 3714 Lab Home Page

Follow this link to the EE 3714 lab home page all sections. You can find the lab policy, lab assignments, and schedule of lab assignments on this page.

Email List

The class EMAIL list will be the one provided by Information Technology Services (ITS). The email list is ece3714-04.fall2001@courses.msstate.edu . All students will be on this list. See the Class EMAIL Faq for further information about how to be added to the list.

WARNING!!! It is your responsibility to make sure that you are on this email list. I will send many homework/test/lecture announcements to this list -- you are responsible for reading the emails sent to this list.

WebCT Course Ware

I will be using a University WWW resource called 'WebCT' for most homework assignments. To access the EE 3714 WebCT course page, go to the WebCT home page , and click on the "Log into myWebCT" option. You will need to use your MSU NetID and password to login into WebCT. If you do not know your MSU Netid, look it up in the online campus directory: http://www.msstate.edu/directory , the MSU NetID is right next to your name. If you have never logged into a WebCT course before, the login name is your MSU NetID, the default passwd is your 6-digit birthdate (mmddyy). Once you have logged into WebCT, use the Password Tool ("Change Password" in upper right corner) to change your password.

Once you are logged into WebCT, you should see under "Courses" on the left-hand side the course "ECE 3714-Digital Devices and Logic Design" (if you do not see this then this means that you have not been added yet - please send me email at reese@ece.msstate.edu and I will add you to the course). Click on the course name to access the course. I will be using WebCT only for online homework quizzes. To take a WebCT quiz, click on the Online Quizzes once you have accessed the course . You will be presented with a list of multiple choice questions. After choosing an answer for a question, click on the 'submit answer' button. This MUST BE DONE FOR EACH QUESTION. Simply choosing an answer does not submit the answer, you must click on the "submit answer" button. There is a chart on the right side that will show how many questions have answers submitted for them; don't leave the quiz until you have answered all of the questions.

Homework Assignments

Most homework assignments (if not all) will be WebCT quizzes. I would suggest that you log onto WebCT, enter the quiz, print out the quiz, then exit your browser without clicking on the "submit" button on the quiz. Work the problems offline, and once you have the answers, re-enter the quiz and enter the answers. When you use the "submit" button to submit the quiz for automated grading, you will be presented with a graded quiz that shows what answers were right or wrong. You can take the quiz twice, the highest grade will be your final score. When we review the quiz in class, you should bring the printed quiz questions to class for review. The WebCT quizzes have a specified cutoff time; after the cutoff time you cannot access the quiz. The cutoff time will always be 6:00 am on the day that it is due. I will usually cover the quiz results on the day that the quiz is due.

  1. Homework #1: Complete the WebCT survey labled Introduction Survey before 6:00 am, Tuesday, August 28. This is an optional assignment and is only meant to familarize you with the WebCT interface. You should work out any problems with using WebCT via this assignment. I will be unsympathic to complaints about WebCT access or problems with WebCT login/password for future WebCT quizzes. Because this is a survey, and not a true quiz, there are no right/wrong answers and you will only be allowed to take this survey once.
  2. Altera Maxplus Tutorial Homework - Due September 13th. Perform the tutorial that is in sections B.1, B.2 of your book. At CLASS TIME, turn in two screen shots - one showing your schematic, and one showing your simulation waveforms.
  3. MAXPLUS_A.ZIP , required by WebCT quiz #6
  4. Combinational Building Block homework - due October 16th, class time. Lab #5 has the truth table for a 'Super Mux'. Implement a 1-bit version of this Super Mux using 2/1 muxes and inverters. The implementation does not have to be minimal. Altera Maxplus has a 2/1 mux implementation called '21mux' that implements the logic equation 'Y = AS + BS'. After you implement a 1-bit version, create a symbol for this schematic, and use this to implement a 4-bit 2/1 Super Mux. Turn in screen shots of both schematics at class time. You may need to tie some inputs of your muxes to '1' and '0'. In maxplus, the part 'VCC' can be used to tie an input to a '1'; the part 'gnd' can be used to tie an input to '0'. The Altera Maxplus 4 to 1 Mux examples covered in class are found in this ZIP ARCHIVE .

Other WebCT quizzes will be posted on the WebCT course page. I will announce in class and via email when they are due. You can also look at the 'availability' dates on the quizzes in order to determine when they are due. You should regularly check the WebCT course page to see if a quiz has been posted. I will not post WebCT quiz dates to this page.

Extra Credit, Fall '01

This document describes how you can earn extra credit in this class that will be applied directly to your test points. I will update this document over time, as well as add ZIP archives that contain test waveforms for the circuits described in the document.

  1. This ZIP ARCHIVE contains the simulation waveform files for the first two problems - an 8-bit decrementer, and 8-bit counter.
  2. This ZIP ARCHIVE contains the simulation waveform files for the second two problems - an 8-bit shifter, and a finite state machine.
  3. This ZIP ARCHIVE contains the simulation waveform files for the third two problems - an 8-bit adder, and an 8-bit adder/subtractor.
  4. This ZIP ARCHIVE contains the simulation waveform files for the fourth problem - a 4x4 combinational multiplier.

Maxplus Software

We will be using a software package called 'Altera Maxplus' for digital logic simulation in this class. Your textbook has a CDROM of this software package on the back cover. We will discuss how to install and use the software in class. Your book also has a good tutorial on the software in Appendix B. Some sample schematics/waveforms that you can experiment with are included in the following ZIP archive (maxplusdemo.zip) .

Lectures, Fall '01

PDF files contains slides printed 3 to a page with room for notes on side.

  1. Introduction to Number systems , PDF file .
  2. Binary Arithmetic, Signed Number representations , PDF file .
  3. Introduction to Boolean Algebra , PDF file .
  4. Real Gates - CMOS, TTL , PDF file .
  5. Mixed Logic , PDF file .
  6. Minterms, Maxterms, Intro to K-maps , PDF file .
  7. Boolean Minimization via K-maps , PDF file .
  8. Multiple Function Minimization, SSN Decoder Lab discussion , , PDF file
  9. Implementing Boolean Logic in Memories, PALs , PDF file
  10. Implementing Boolean equations in VHDL, PDF file
  11. Combinational Building Blocks , PDF file
  12. Flip Flops, Latches , PDF file
  13. Timing for Flip Flops, Latches , PDF file
  14. Sequential Building Blocks, , PDF file .
  15. General Finite State Machine Design , PDF
  16. Discussion of Lab assignment: Finite State Machine based upon Student ID Number , PDF
  17. Misc topics on FSM/Datapath control , PDF
  18. Dice Game implementation in 22V10 PLDs , PDF
  19. More discussion on Dice Game details , PDF
  20. An Introduction to High Level VHDL statements via the dicegame example , PDF
  21. An Introduction to FPGAs , PDF

Sample Tests

  1. Test 1, Solutions, Fall '99 (pdf)
  2. Sample Test #2, Fall '99 (pdf) ,
  3. Sample Test #3, Fall '99 (pdf) , Sample Test #3 Solutions, Fall '99 (pdf)
  4. Sample Test #4, Fall '99 , Sample Test Solutions #4, Fall '99 , Sample Test #4 Diagrams
  5. Solutions for Test #1, Spring 2000 (PDF)
  6. Solutions for Test #2, Spring 2000 (PDF)
  7. Solutions for Test #3, Spring 2000 (PDF)
  8. Solutions for Test #4, Spring 2000 (PDF)
  9. Solutions for Test #1, Fall 2001 (PDF)
  10. Solutions for Test #2, Fall 2001 (PDF)
  11. Solutions for Test #3, Fall 2001 (PDF)

Lectures, Fall '00

PDF files contains slides printed 3 to a page with room for notes on side.

  1. Introduction to Number systems , PDF file .
  2. Binary Arithmetic, Signed Number representations , PDF file .
  3. Introduction to Boolean Algebra , PDF file .
  4. Real Gates - CMOS, TTL , PDF file .
  5. Mixed Logic , PDF file .
  6. Minterms, Maxterms, Intro to K-maps , PDF file .
  7. Boolean Minimization via K-maps , PDF file .
  8. Multiple Function Minimization, SSN Decoder Lab discussion , , PDF file
  9. Implementing Boolean Logic in Memories, PALs , PDF file
  10. Implementing Boolean equations in VHDL, PDF file
  11. Combinational Building Blocks , PDF file
  12. Flip Flops, Latches , PDF file
  13. Timing for Flip Flops, Latches , PDF file
  14. Sequential Building Blocks, , PDF file .
  15. General Finite State Machine Design , PDF
  16. Discussion of Lab assignment: Finite State Machine based upon Student ID Number , PDF
  17. Misc topics on FSM/Datapath control , PDF
  18. Dice Game implementation in 22V10 PLDs , PDF
  19. More discussion on Dice Game details , PDF
  20. An Introduction to High Level VHDL statements via the dicegame example , PDF
  21. An Introduction to FPGAs , PDF
  22. Revisit Arithmetic Operations (Add, Add/Sub, increment, comparison), PDF

Printing out Lectures

If you have Powerpoint on your PC, you can download the Powerpoint file (.PPT file) itself from the table of contents slide of each lecture. When you print the file from within Powerpoint, there is a choice window near the bottom of the print screen that says "Print What". You can either choose "Slides" (prints 1 slide per page), or "Handouts, 2 per page", "Handouts, 3 per page", "Handouts, 6 per page". Printing multiple slides per page is probably the best way to go. For the Word/PPT 2000 version, the "6 per page" option is in a different menu from the other options.

Datasheets

Data sheets for TTL parts are available via the WWW at this link . This is a search engine; enter a part number like "7400" and you will given a general information sheet plus a link to PDF file that has the complete datasheet (PDF file can only be read with Adobe acrobat). You may need to try technology specific variations on the numbers like "74LS00" instead of "7400", or just type in the last part and omit the '74' (i.e. for 74181, use just 181). Several parts may show up like "SN54LS181", "SN74S181", etc - usually all of these will be functionally equivalent and have the same pinout UNLESS SPECIFICALLY noted on the datasheet. General information on data sheets on CDROM can be found here .

Other Links

  1. SSN Decoder PreLab Requirements
  2. SSN Combinational Decoder Lab : Form for VHDL compilation/simulation, JEDEC file production
  3. SSN Finite State Machine Lab: Prelab Requirements, Lab Schedule for rest of the semester
  4. SSN Finite State Machine Lab : Form for VHDL compilation/simulation, JEDEC file production
  5. DiceGame Lab Assignment
  6. General Form for VHDL compilation to JEDEC file

Other Textbook References

It always helps to have more than one point of view on a subject. Here are some additional references:

  1. Fundamentals of Logic Design , Charles Roth (ISBN 0534954723) : This is a very good textbook on basic Logic Design. The best thing about this book is the number of examples and exercises that it contains.
  2. Contemporary Logic Design , Randy Katz (ISBN 0805327037) : Another good textbook on introductory logic design.