1.University of Strasburg (FRANCE) VHDL Archive

Archive List / readme

• ISCAS VHDL Model (ISCAS85/89) / readme

• Misc
• ACRONYM LIST
• VHDL Analog Extension (IEEE 1076.1)
• VHDL Modeling for Analog-Digital Hardware Designs
• Comparison Random Number Generator (ada) / PDF

• Models.VHDL
• 2901.vhdl (files)  /  2910.vhdl (files)  /  8251.vhdl (files)
• DP32.vhdl (readme)  /  gl85erm.vhdl (readme)  /  kalman.vhdl (files)
• lfsr.vhdl (pdf)  /  multiplier.2.vhdl (pdf)  /  Serial-adder.vhdl (pdf)
• SN54S151.vhdl (pdf)  /  uart-mem-and-error-by-cohen (readme)
• arms-counter.vhdl  /  barrel.vhdl  /  coelho.bib.vhdl
• diffeq.vhdl  /  dlx.vhdl  /  dram_8_512.vhdl  /  eeserv.ee.umanitoba.ca
• ellipf.vhdl  /  float_adder  /  gcd_vhdl  /  gl85.vhdl
• I80386.vhdl  /  IEEE_1149  /  Mark2.vhdl  /  MASI.vhdl
• mouse1.vhdl  /  mouse2.vhdl  /  multiplier.1.vhdl
• Parity-set.vhdl  /  reg4.vhdl  /  tlc.vhdl  /  traffic-light.vhdl
• uceng.uc.edu  /  Z80.vhdl  /  zycad.vhdl

• Packages.vhdl
• Al_Gilman_pack  /  Analog_lib  /  EIA_Types  /  IEEE_1164.vhdl
• maths.vhdl  /  petri.vhdl (readme)  /  queue.vhdl (readme)
• random1.vhdl  /  random2.vhdl  /  spice_with_vhdl
• Vantage_pack  /  VHDL_stand.comp.lib  /  vhdl_synth.package (history)
• WAVES

• Papers
• Guidelines for writing VHDL Models in a teamwork environment
• Armstrong book  /  EPIC2  /  ESA Report
• Femto-VHDL.JVTassel (readme)
  John Van Tassel's PhD  "Femto-VHDL: The Semantics of a Subset of VHDL and its Embedding in the HOL Theorem-Prover"
• IEEE Excerpt  /  recursive.Ashenden  /  Tufts university (readme)
• VHDL Cookbook (readme) - PDF Document
  The VHDL Cookbook  First Edition (July 1990)  (c) 1990, Peter J. Ashenden

• Results at ERM-MACAO

• Synthesis VHDL Model
  These examples of syntisable designs are available on VHDL.ORG proposed by NAVABI (navabi@ece.neu.edu)
  (RTL models are available only here)

ORIGINAL ---- Behevioral definitions
RTL ---- RTL synthesis (Y.HERVE ERM/PHASE with EXEMPLAR/CORE)
HARDWARE ---- structural (pAsic targetted)
TESTING/LIST ---- listfil output of tests (V-SYSTEM/MODELTECH ?)
TESTING/TEST ---- testbenchs
SIM_LIB/PAsic20.VHD ---- gate models for structural simulation

• Tests for VHDL / readme

• Util for VHDL
• VHDL Beautifier  /  EMACS Mode  /  Frontend  /  nicifier
• pretty_printer_ADA  /  profiler (readme)  /  the_final_pretty_printer
• UC VHDL - VHDL Grammar (yacc) (readme)  /  VHDL Parser (Prolog)
• vhdl_1_2_1.vhdl  /  VHDL2C (Linux Binary)  /  VHDL93 BNF  /  VMKR & VSplit

2-1.European Space Research and Technology Centre
Microelectronics: Space Applications and Design Methodology / (Here)

2-2.European Space Agency VHDL Archive

• European Space Agency VHDL Repository
• Included Directory: Document  /  Source Code  /  Temporary  /  Tools

• ERC32 Processor
• Cross Compiler (GNU)
• VHDL Model
• Testbench
• Documents

3.University of Stuttgart VLSI Design Course

• VLSI_course / readme
• DLXS-P.beta

4.IFIP WG10.5 Benchmark Circuits for Hardware Verification / (Here) / FTP Site

5.Courses and Tutorials

• VLSI Design Course using the Synthesizable DLX 32-bit Generic RISC Processor
  Created by : M. Gumm, University of Stuttgart (c) 1995

• Logic Synthesis using VHDL
  Created by : Dimitris Phoukas

• Computer Aids for VLSI Design
  Second Edition by Steven M. Rubin

• A VHDL Methodology for FPGAs (Here)
  Michael Gschwind, Valentina Salapura / {mike,vanja}@vlsivie.tuwien.ac.at / Institut f? Technische Informatik

• Navigating VHDL (Here)
  This chapter provides an introduction to the basic language constructs in VHDL; defining logic blocks, structural, dataflow and behavioral descriptions, concurrent and sequential functionality, design partitioning and more.

6.VHDL Papers & Models

• Papers
• Femto-VHDL: The Semantics of a Subset of VHDL and its Embedding in the HOL Proof Assistant
  by John Peter Van Tassel, Gonville and Caius College
• Recursive and Repetitive Hardware Models in VHDL
  Peter J. Ashenden
• RASSP Benchmark-1 and -2: A Preliminary Assessment
  A. H. Anderson, G. S. Downs, G. A. Shaw, Lincoln Laboratory, Massachusetts Institute of Technology
• Reuse-Oriented Model Year Architectures for Rapid Prototyping
  G. Caracciolo and J. Pridmore, Lockheed Martin Advanced Technology Laboratories
• Rapid Design and Exploration of Signal Processing Systems using a VHDL Model Generator Based Paradigm 1
  Scott R. Powell and Thomas M. Cesear
• Integration of DFT into RASSP
  John Evans, Lockheed Martin Advanced Technology Laboratories
• A Framework for the Development of Hybrid Models
  Moshe Meyassed, Robert McGraw, James Aylor, Robert Klenke, Ronald Williams, University of Virginia
  Fred Rose, John Shackleton, Honeywell Technology Center
• Implementation of the RASSP SAR Benchmark on the Intel Paragon
  Curtis P. Brown, Richard A. Games, John J. Vaccaro, The MITRE Corporation,
• RASSP Technology Insertion into the Synthetic Aperture Radar Image Processor Application
  Junius Pridgen, Richard Jaffe, William Kline, Lockheed Martin Advanced Technology Laboratories
• Approximate Processing and Incremental Re nement Concepts
  J. Winograd, J. Ludwig, H. Nawab, A. Chandrakasan, A. Oppenheim, Massachusetts Institute of Technology, RLE, Cambridge, MA 02139
• Workflow Modeling for Implementing Complex,CAD-Based, Design Methodologies
  J. Stavash and J. Wedgwood, M. Forte
• VHDL Modeling, Test, and Distribution
  Vincent L. Sanders, Robert B. Reese, Aubrey K. Knight, J. Scott Calhoun, Mississippi State University
• Automated Generation of Accurate VLSI Behavioral Processor Models for Simulation and Synthesis
  Yong-kyu Jung 1 , Vijay K. Madisetti, Georgia Tech
• Integrated Process Control and Data Management in RASSP Enterprise Systems
  John Welsh, Biju Kalathil and Bipin Chadha Mary Catherine Tuck and William Selvidge,Elisa Finnie, Arne Bard
• Symbolic Veri cation of Sequential Circuits Synthesized with CALLAS 1 ; 2 Extended Summary
  Thomas Filkorn Michael Payer 3 Peter Warkentin
• Model Checking in Industrial Hardware Design
  Jorg Bormann, Jorg Lohse, Michael Payer and Gerd Venzl, Siemens Corporate R&D
• Formal Veri cation of a PowerPC TM Microprocessor
  David P. Appenzeller, Andreas Kuehlmann
• VHDL-Translation for BDD-Based Formal Verification
  Jorg Lohse, Jorg Bormann, Michael Payer, and Gerd Venzl
• A VHDL Speci cation of a Shared Memory Parallel Machine for Babel
  W. Hansy, J.J. Ruzz, F.S aenzz, S. Winklery
• The VHDL Scout Handbook - 3'rd Edition
  COMPASS Design Automation

• Virtual Socket Interface
• VSI Alliance^(TM) Architecture Document 1.0

7.RASSP (Rapid-Prototyping of Application Specific Signal Processors) VHDL Page / (Here)

8.Microsystems Prototyping Laboratory (MPL)
Mississippi State University / National Science Foundation / (Here)

• MPL Distributions (Here)
• VHDL Model Collection - MPL's vhdl model collection includes various commercial off the shelf parts including fifo's, Xilinx fpga, pld's, rams, and others. (Here)
• SCMOS/GCMOS Standard Cell Library - Here you will find the MSU scmos standard cell library intended for prototyping use via the MOSIS VLSI Fabrication Service. We also provide some leafcells in MOSIS technologies for use with the Mentor Memory Builder program. (Here)
• 1750a Processor - Synthesizable VHDL Models (Requires Passwd) - This is MPL's 1750a Processor Models. (Here)

• MPL Education (Here)
• Classes
  VHDL Class (Here)
  EE 4253/6253, Principles of VLSI Design (Here)
  EE 8223, Analog IC Design (Here)
• Tutorials
  VHDL Synthesis Tutorial (Here)
• Documentation
  DLX Implementation at MSU (Here)
• Cadence Partner
  MSU/ Cadence University Alliance Program Member (Here)

9.The Hamburg VHDL archive / (Here)

10.Department of ECECS: University of Cincinnati VHDL Archive / (Here)

11.VHDL Resources...

• Peter Ashenden
  Department of Computer Science / University of Adelaide, SA 5005 / Australia
• A Superscalar Version of the DLX Processor (Here)
• Bob Reese's Home Page (Here)
  Director of the Microsystems Prototyping Laboratory associated with the Mississippi State University/National Science Foundation Engineering Research Center for Computational Field Simulation.
• Daniel H. Linder's Home Page (Here)
  An assistant professor in the Department of Electrical and Computer Engineering at Mississippi State University.
• A Strategic Process for System Level Verification / On Line Seminar (Required the Real Player)
  Author: Janick Bergeron, VP of Technical Wisdom, Qualis Design / Publisher: Qualis Design Corporation / Publication Date: 7 October, 1998
• QUALIS Library (Here)

• 1995 High Level Synthesis Design Repository (Here)
  Coordinator: Nikil Dutt, U.C. Irvine / Authors: Preeti Ranjan Panda, U.C. Irvine / Nikil Dutt, U.C. Irvine
  First Created: 18 January 95 / Last Updated: 25 January 95
• Tokyo Electrical Engineering faculty - TTL and behavioral models (Here)
• Reto Zimmermann's Home Page (Here)
• GoodKook's VHDL Model Archives (Here)
• The underlying grammar (a slightly simplified VHDL93 grammar) - BNF for VHDLParser.jj (Here)

• department of electrical and computer engineering hardware description language research and development (Here)
• Michael R. Mayer, UM-Rolla, EE Dept. (Here)
  mc8051 - Both behavioural and structural (synthesizable!) models of the 8051 controller. The model comes with testbench and several .hex files.

12.EDIF LPM - Library of Parameterized Modules / (Here)

13.VHDL CODE LAND

VHDL CODE LAND is a communication environment provided for the modeling of digital systems and components. It encompasses a client-side VHDL tutorial (lectures and lessons), a presentation of methods and tools concerning VHDL modeling and an extensive set of links allowing to view (and use) foreign VHDL tutorials, component libraries, demonstration tools, etc.  VCL is a useful framework for your VHDL based modeling activities

• Welcome to IRESTE group
• Welcome to EMN group
• Welcome to CTI group
• Welcome to ISMRA group
• TEMIC
• GUEST

14.Welcome to Doulos / (Here)

For high quality VHDL and Verilog training For HDL-based FPGA and ASIC design leadership For true expertise in High Level Design