From: vhdlcohen@aol.com (VhdlCohen) Copy of ftp.rahul.net in subdirectory " pub/quanta/bcohen" the following VHDL files: errinj.vhd Error injector model erinj_tb.vhd Error injector testbench uartxmt.vhd Simple UART transmitter model (synthesizable) uartrx.vhd Simple UART receiver model (synthesizable) memory.vhd Memory model initialized from a file The error injector model is useful in certain applications such as the testing of components which perform error detection based the value of their interface signals. This model is also interesting for educators because it provides one of the few times a "wait for 0 ns;" construct is necessary. My general recommendation is to avoid the "wait for 0 ns;" to make up for delta times. However, this model uses this construct to emulate a "break". This model also demonstrates another application of the "generate" statement. The testbench file demonstrates the component instantiation statement, and the configuration statement. These models were previously distributed to this group. However, if you fail to FTP them or fail to find them in this newsgroup, send me a note (preferably at "bcohen@ccgate.hac.com"), and I'll email the models you request. --============================================= -- Ben Cohen, "VHDL Coding Styles and Methodologies ", -- ISBN 0-7923-9598-0 Kluwer Academic Publishers. -- Hughes Aircraft Co, RE- R1/B507 -- 2000 East Imperial Hwy -- El Segundo, Ca, 90245 -- (310) 334-7389, fax: (310) 334-1749 --=============================================