-------------------------------- VHDL Modeling for Analog-Digital Hardware Designs -------------------------------- Balsha R. Stanisic International Business Machines Application Business Systems 453/040-2 Hwy 52 & 37th St. Rochester, MN 55901 Phone: (507) 253-1350 Mark W. Brown International Business Machines Application Business Systems 29K/040-2 Hwy 52 & 37th St. Rochester, MN 55901 Phone: (507) 253-4001 -------------------------------- This material contains excerpts from a paper published in the IEEE ICCAD-89 Proceedings pages 184-187 - copyright IEEE 1989. -------------------------------- -------------------------------- -- Abstract -------------------------------- Historically the analog and digital partitions of a hardware design have been modeled in different languages and simulated using separate simulators. Each simulation has been adequate within its partition, but these partitions could not be combined. Simulating the analog-digital interaction and assuring that it reflects the physical analog-digital interconnection is required to insure a good design. The VHSIC Hardware Description Language (VHDL) and its associated simulator can model and simulate the analog-digital interaction assuring that it reflects the analog-digital physical interconnection because VHDL can describe both analog and digital circuits behaviorally and structurally. This paper describes techniques for simulation modeling and a physical design verification methodology for assuring simulation and interconnection correspondence. Following the introductory material, details of the simulation model are presented. Then a description of a physical design verification methodology is given, followed by results from current designs and finally, "key" points are summarized. The text of the paper is not included on the bulletin board, however, the 7.2 version of the VHDL source for an analog amplifier follows: -------------------------------------------------------------- -- Basic Amplifier Behavioral -------------------------------------------------------------- WITH PACKAGE analog_data_structure; USE analog_data_structure; WITH PACKAGE analog_passive_behaviors; USE analog_passive_behaviors; -- interface ENTITY amplifier ( vinp : IN analog_signal; vinn : IN analog_signal; aref : IN analog_reference_aref; vout : BUFFER analog_signal ) IS GENERIC ( gain : analog_vv_gain; vcmo : analog_v_level; vout_min : analog_v_level; vout_max : analog_v_level; r : analog_component; c : analog_component) ASSERT( (r.val > 0.0) AND (c.val > 0.0) ) REPORT "ERROR: R and C must be > 0.0" SEVERITY failure; ASSERT( vout_max.val > vout_min.val ) REPORT "ERROR: vout_max must be > vout_min" SEVERITY failure; END amplifier; -- body ARCHITECTURE amplifier_behavior OF amplifier IS B2: BLOCK INITIALIZE analog_signal TO (val => 0.0, kind => v); SIGNAL ac_in, ideal_vout, pvout: analog_signal; BEGIN ac_in.val <= (vinp.val - vinn.val) * 0.5; ideal_vout.val <= vcmo.val + (ac_in.val * gain.val); vout <= rc(r, c, pvout, ideal_vout, vout_min, vout_max); pvout <= vout AFTER analog_time_delta; --analog tstep END BLOCK; END amplifier_behavior; -------------------------------------------------------------- -- Basic analog passive behavior package with low pass behavior -------------------------------------------------------------- WITH PACKAGE analog_data_structure; USE analog_data_structure; PACKAGE analog_passive_behaviors IS -- -- function for RC - Low Pass -- FUNCTION rc ( r : analog_component; c : analog_component; pred1_vout : analog_signal; vin : analog_signal; clamp_lo : analog_v_level; clamp_hi : analog_v_level) RETURN analog_signal IS VARIABLE tau : real; VARIABLE vout : analog_signal; BEGIN tau := ( r.val * c.val); vout.val := ( (pred1_vout.val * tau) + (vin.val * analog_time_delta_real) ) /(tau + analog_time_delta_real); -- clamp limits IF (vout.val > clamp_hi.val) THEN vout.val := clamp_hi.val; ELSIF (vout.val < clamp_lo.val) THEN vout.val := clamp_lo.val; END IF; vout.kind := v; RETURN vout; END rc; END analog_passive_behaviors; -------------------------------------------------------------- -------------------------------------------------- -- Basic Analog Data Structure -------------------------------------------------- WITH PACKAGE analog_bus_res_function; USE analog_bus_res_function; PACKAGE analog_data_structure IS -- analog time step CONSTANT analog_time_delta : time := 100ps; CONSTANT analog_time_delta_real: real := 0.1; --ns -- analog signal TYPE signal_mode IS (v, i); TYPE analog_signal IS RECORD val: brf_real; kind: signal_mode; END RECORD; -- analog reference TYPE analog_reference_aref IS RECORD val: real; END RECORD; -- analog component TYPE component_element IS (res, cap, ind); TYPE analog_component IS RECORD val: real; kind: component_element; END RECORD; -- analog threshold levels TYPE analog_v_level IS RECORD val: real; END RECORD; -- analog gain TYPE analog_vv_gain IS RECORD val: real; END RECORD; END analog_data_structure; -------------------------------------------------- ---------------------------------------------------- -- Basic Bus Resolution Function for Current Summing ---------------------------------------------------- PACKAGE analog_bus_res_function IS -- TYPE analog_val IS ARRAY ( integer RANGE<> ) OF real; -- FUNCTION analog_brf_val (data_array: analog_val) RETURN real IS VARIABLE i : integer; VARIABLE result : real; BEGIN result := data_array(data_array'LOW); FOR i := (data_array'LOW + 1) TO (data_array'HIGH) LOOP result := ( result + data_array(i) ); END LOOP; RETURN result; END analog_brf_val; -- SUBTYPE brf_real IS ATOMIC analog_brf_val real; END analog_bus_res_function; ----------------------------------------------------