Xilinx CPLD에서 Flip-Flop의 초기상태 값을 설정하는 방법은...? (2004.7.18)
Metastability Delay and Mean Time Between Failure in Virtex-II Pro FFs (2004.2.23)
Floorplanning for High-Performance FPGA Designs, Stephen Wasson, March 1995, Integrated System Design (2017.3.24)
Design Tips for High-Performance FPGA Design, Stephen Wasson, October 1994, ASIC & EDA (2017.3.24)

Six Easy Pieces (Non-Synchronous Circuit Tricks) (2004.2.23)
What are Virtex and Spartan-II I/O Pins Doing? (2004.2.23)
Locking Logic to a Single Xilinx Virtex LUT (2003.1.26)