A VHDL Template for Combinational Logic

entity  model_name is

      port  (

               list of inputs and outputs );

    end model_name;

  architecture  arch_name  of model_name is

    begin

        concurrent statement 1

        concurrent statement 2

         ... concurrent statement N;

    end  arch_name;

All of the text not in italics are VHDL keywords.    VHDL is NOT case sensitive. (ENTITY is same as entity is same as EnTiTy).

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