Xilinx UCF (User Constraint File) ÆÄÀÏÀÇ ÀÌÇØ...


 

 UCF FileÀÇ ÀÌÇØ...

(1999.5.1)

 

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BASIC UCF SYNTAX EXAMPLES V2.1.6

"#" µµÇüÀº ÁÖ¼®¹®ÀÚÀÔ´Ï´Ù.  ÀÌ ¿¹Á¦ ÆÄÀÏÀ» »ç¿ëÇÏ·Á¸é, ÇÊ¿äÇÑ ±Ô°ÝÀ» ã¾Æ¼­, ÇàÀÇ ½ÃÀÛ¿¡ ÀÖ´Â ÁÖ¼® Ç¥±â ¿ë ¹®ÀÚ(#)¸¦ Áö¿ì½Ã±æ ¹Ù¶ø´Ï´Ù.  ¸¸ÀÏ ÇÊ¿äÇÏ´Ù¸é ´ç½ÅÀÇ µðÀÚÀο¡ ¸Â°Ô ÇàÀÇ ³»¿ëÀ» ¼öÁ¤ÇϽʽÿÀ.

 

TIMING SPECIFICATIONS

ŸÀÌ¹Ö ±Ô°ÝÀº Àüü µðÀÚÀÎ(global)¿¡ Àû¿ëÀÌ µÉ ¼ö Àְųª ¿©·¯ºÐÀÇ µðÀÚÀγ»ÀÇ Æ¯Á¤ ±×·ì(time groups)¿¡ Àû¿ëÀÌ µÉ ¼ö°¡ ÀÖ½À´Ï´Ù.  Å¸ÀÓ ±×·ìÀº µÎ °¡Áö ±âº»ÀûÀÎ ¹æ¹ýÀ¸·Î ¼±¾ðµÉ ¼ö ÀÖ½À´Ï´Ù.

  • ¹æ¹ý 1 : ³×Æ® À̸§À» ÀÌ¿ëÇÏ¿©, my_net¶ó´Â net°¡ logic_grp¶ó´Â group¿¡ ¼ÓÇØ ÀÖ´Â ¸ðµç logic¿¡ ¿¬°áÀÌ µÇ¾î ÀÖ´Ù¸é ¿¹¸¦ µé¸é
    NET my_net TNM_NET = logic_grp ;
  • ¹æ¹ý2 : 'TIMEGRP' ¶ó´Â key word¸¦ »ç¿ëÇÏ¿© ±×·ìÈ­ ÇÏ°í ¿©·¯ºÐ µðÀÚÀÎÀÇ ·ÎÁ÷ÀÇ À̸§À» »ç¿ëÇÏ¿© ¼±¾ðÇÑ´Ù.  ¿¹¸¦ µé¸é
    TIMEGRP group_name = FFS ("U1/*");
    U1À¸·Î ºÒ¸®´Â °èÃþ±¸Á¶ ¾È¿¡ ÀÖ´Â ¸ðµç flip-flopÀ» À§ÇÑ 'group_name'À̶ó ºÒ¸®´Â ±×·ìÀ» ¸¸µç´Ù.  Wildcards °¡ »ç¿ë °¡´ÉÇÕ´Ï´Ù.

GroupingÀº ¿©·¯ºÐÀÌ software¿¡°Ô µðÀÚÀÎÀÇ ¾î´À ºÎºÐÀÌ ¾î¶² ¼Óµµ·Î µ¿ÀÛÇÏ´ÂÁö¸¦ ¾Ë·Á Áֱ⠶§¹®¿¡ ¸Å¿ì Áß¿äÇÕ´Ï´Ù.  ´ÜÁö ÇϳªÀÇ Å¬·°À» °¡Áö´Â µðÀÚÀÎÀÇ Áß¿ä ºÎºÐÀ» À§Çؼ­´Â °£´ÜÇÑ ±¤¿ª Á¦ÇÑ »çÇ×À» »ç¿ëÇÏ¸é µË´Ï´Ù.

¿©·¯ºÐÀÌ »ç¿ëÇÏ´Â grouping constraintÀÇ ÇüÅ´ ¿©·¯ºÐÀÌ »ç¿ëÇÏ°í ÀÖ´Â ÇÕ¼º Åø¿¡ µû¶ó º¯ÇÒ ¼ö ÀÖ½À´Ï´Ù.  Foundation Express´Â ¹æ¹ý2°¡ ´õ¿í ÁÁ½À´Ï´Ù.

 

Internal to the device clock speed specifications - Tsys

 

Single Clock

 

PERIOD TIME-SPEC

ÁÖ±â(period) ±Ô°ÝÀº register, latch, ¶Ç´Â ±âÁØ net(excluding pad destinations)¿¡ ÀÇÇØ µ¿±âÈ­ µÇ´Â synchronous RAM¿¡¼­ ½ÃÀÛÇϰųª ³¡³ª´Â ¸ðµç ŸÀÌ¹Ö °æ·Î¸¦ ´ã´çÇÕ´Ï´Ù.  ¶ÇÇÑ ´Ù¸¥ ¿ä¼Ò(ex. flip flops, pads, etc...)µé¿¡ °ü·ÃµÈ synchronous elementÀÇ setup ¿ä±¸»çÇ×(requirement)µµ ´ã´çÇÕ´Ï´Ù.
NOTE: ½Ã°£¿¡ ´ëÇÑ ±âº» ´ÜÀ§´Â ³ª³ë¼¼ÄÁµå(nanoseconds)ÀÔ´Ï´Ù.
NET clock PERIOD = 50ns ;

-OR-

 

FROM:TO TIME-SPECs

FROM:TO style timespecsÀº time groups»çÀÌÀÇ °æ·Î¸¦ Á¦ÇÑ(constrain)ÇÏ´Â µ¥ »ç¿ëµÇ¾î Áý´Ï´Ù.  NOTE: RAMS, FFS, PADS, LATCHES¿Í °°Àº keywords(¿¹¾à¾î)´Â µðÀÚÀο¡ À־ °¢ ÇüÅÂÀÇ ¸ðµç ¿ä¼Ò¸¦ Á¤ÀÇÇÏ´Â µ¥ »ç¿ëÇϵµ·Ï ¹Ì¸® Á¤ÀÇ°¡ µÇ¾î ÀÖ½À´Ï´Ù.  »ç¿ë¹æ¹ýÀº ¸ÕÀú ¿øÇÏ´Â TIME GROUPÀ» Á¤ÀÇÇÏ°í TIMESPECÀ̸§À» Á¤ÀÇÇÏ¿© »ç¿ëÇÏ½Ã¸é µË´Ï´Ù.

TIMEGRP RFFS = RISING FFS ("*"); // creates a rising group called RFFS
TIMEGRP FFFS = FALLING FFS ("*"); // creates a falling group called FFFS
À§ÀÇ µÎ ¹®ÀåÀº RFFS¿Í FFFS¶ó´Â TIME GROUPÀ» Á¤ÀÇÇÑ °ÍÀÔ´Ï´Ù.

TIMESPEC TSF2F = FROM : FFS : TO : FFS : 50 ns; // Flip-flips with the same edge
TIMESPEC TSR2F = FROM : RFFS : TO : FFFS : 25 ns; // rising edge to falling edge
TIMESPEC TSF2R = FROM : FFFS : TO : RFFS : 25 ns; // falling edge to rising edge
À§ÀÇ ¹®Àåµé¿¡¼­ TIMESPEC ´ÙÀ½¿¡ ³ª¿À´Â °ÍÀÌ TIMESPEC À̸§ÀÌ µÇ´Â µ¥, ¿©±â¼­ ±ÔÄ¢Àº TS´Â Ç×»ó ³ª¿À´Â °ÍÀÌ¸ç ³ª¸ÓÁö´Â »ç¿ëÀÚ°¡ ¾Ë¾Æ¼­ ¸¶À½´ë·Î ÇÏ½Ã¸é µË´Ï´Ù.  ¿¹¸¦ µé¸é TS_SP1, TS01, TS_FIRSTÀÔ´Ï´Ù.  À§ÀÇ ¹®Àå¿¡¼­ ¿ì¸®´Â TSF2F´Â FLIPFLOP TO FLIPFLOP¿¡ ´ëÇÑ TIMESPECÀÓÀ» ¾Ë ¼ö ÀÖ½À´Ï´Ù.

 

Multiple Clocks

'PERIOD'¿Í 'FROM:TO' ÇüÅÂÀÇ time specification¿¡ ´ëÇÑ Á¶ÇÕÀÌ ÇÊ¿äÇÕ´Ï´Ù.
NET clock1 TNM_NET = clk1_grp ;
NET clock2 TNM_NET = clk2_grp ;

À§ÀÇ µÎ ¹®ÀåÀ» Çؼ®Çϸé clock1 net¸¦ clk1_grp¶ó°í net¿¡ timespec¸¦ Á¤ÀÇÇÕ´Ï´Ù.  Clock2 net´Â clk2_grp¶ó´Â timespecÀ» Á¤ÀÇÇÕ´Ï´Ù.

TIMESPEC TS_clk1 = PERIOD : clk1_grp : 50 ;
TIMESPEC TS_clk2 = PERIOD : clk2_grp : 30 ;
TIMESPEC TS_ck1_2_ck2 = FROM : clk1_grp : TO : clk2_grp : 50 ;
TIMESPEC TS_ck2_2_ck1 = FROM : clk2_grp : TO : clk1_grp : 30 ;

À§ÀÇ ¹®ÀåÀ» Çؼ®Çϸé TS_clk1À̶ó´Â TIMESPECÀº clk1_grp¶ó´Â TIMEGROUP¿¡ ÁÖ±â 50NSÀ» ÇÒ´çÇÏ°í ÀÖÀ½À» ¾Ë ¼ö ÀÖÀ¸¸ç, ³ª¸ÓÁöµµ CLK1 °ú CLK2»çÀÌÀÇ ½Ã°£ °ü°è¸¦ Á¤ÀÇÇÏ°í ÀÖ½À´Ï´Ù.

 

CLOCK TO OUT specifications - Tco

 

OFFSET TIME-SPEC

¿©·¯ºÐÀÇ clock-to-out timing specifications¿¡ clock buffer/routing delay¸¦ ÀÚµ¿ÀûÀ¸·Î Ãß°¡ ÇÒ ¼ö ÀÖµµ·Ï, OFFSET constraints¸¦ »ç¿ëÇϽʽÿÀ.  ¿¹¸¦ µé¾î maximum clock-to-out (Tco)°¡ 25 ns À̸é:

NET out_net_name OFFSET = OUT 25 AFTER clock_net_name ;

-OR-

 

FROM TO TIME-SPECs

TIMESPEC TSF2P = FROM : FFS : TO : PADS : 25 ns;
FROM: FFS : TO: PADS constraints´Â flip flop ±× ÀÚü¿¡¼­ Áö¿¬ºÐ¼®(dalay analysis)À» ½ÃÀÛÇϸç Ŭ·° ÀÔ·ÂÇÉ¿¡¼­ ½ÃÀÛÇÏÁö ¾Ê½À´Ï´Ù.  clock-to-out constraintÀ» ¸¸µé±â À§ÇØ, ±Ç°íÇÏ´Â ¹æ¹ýÀº OFFSET constraintÀ» »ç¿ëÇÏ´Â °ÍÀÔ´Ï´Ù.

 

Pad to Flip-Flop speed specifications - Tsu

 

OFFSET TIME-SPEC

¿©·¯ºÐÀÇ ÀÔ·Â setup timing specifiactions¾È¿¡ clock delay¿¡ ´ëÇÑ ÇÕ»êÀ» ÀÚµ¿ÀûÀ¸·Î ³ÖÀ¸·Á¸é, OFFSET constraintsÀ» »ç¿ëÇϽʽÿÀ.  For an input where the maximum setup time is 25 ns:
NET in_net_name OFFSET = IN 25 BEFORE clock_net_name ;

-OR-

 

FROM TO TIME-SPECs

TIMESPEC TSP2F = FROM : PADS : TO : FFS : 25 ns;
FROM: PADS : TO: FFS constraints´Â clock path¿¡ ´ëÇÑ ¾î¶² Çջ굵 ÃëÇÏÁö ¾Ê´Â °ÍÀ» ÁÖÀÇÇϽʽÿÀ.  input setup time constraintÀ» ¸¸µå´Â ±Ç°í ¹æ¹ýÀº OFFSET constraintÀ» »ç¿ëÇÏ´Â °ÍÀÔ´Ï´Ù.

 

Pad to Pad speed specifications - Tpd

 

FROM TO TIME-SPECs

TIMESPEC TSP2P = FROM : PADS : TO : PADS : 125 ns;

 

Other timing specifications

 

TIMING IGNORE

¸¸ÀÏ ¿©·¯ºÐÀÌ path(°æ·Î)ÀÇ timingÀ» ¹«½ÃÇÒ ¼ö ÀÖ´Ù¸é, Timing Ignore(TIG)À» »ç¿ëÇϽʽÿÀ.  ÁÖÀÇ »çÇ× : "*" ¹®ÀÚ´Â ¹ö½º À̸§¿¡ »ç¿ëµÉ ¼ö ÀÖ´Â, wild-cardÀÔ´Ï´Ù.  "?"´Â ÇÑ ¹®ÀÚ¿¡ ´ëÇØ wild-card·Î »ç¿ëÇÒ ¼ö ÀÖ´Â ¹®ÀÚ ÀÔ´Ï´Ù.

Ignore timing of net reset_n:
NET : reset_n : TIG ;

Ignore data_reg(7:0) net in instance mux_mem:
NET : mux_mem/data_reg* : TIG ;

Ignore data_reg(7:0) net in instance mux_mem as related to a TIMESPEC named TS01 only:
NET : mux_mem/data_reg* : TIG = TS01 ;

Ignore data1_sig and data2_sig nets:
NET : data?_sig : TIG ;

 

PATH EXCEPTIONS

¿©·¯ºÐÀÇ µðÀÚÀÎÀÌ Ãâ·ÂÀÌ ´Ù¸¥ Ãâ·Âº¸´Ù ´õ¿í ´ÊÀ» ¼ö ÀÖ´Ù¸é ¿©·¯ºÐÀº OUT_DATA(7:0)°ú irq_n Ãâ·Â¿¡ ´ëÇÑ ´ÙÀ½ ¿¹¿Í °°ÀÌ TIMESPEC¸¦ Á¤ÀÇ ÇÒ ¼ö°¡ ÀÖÀ» °ÍÀÔ´Ï´Ù.
TIMEGRP slow_outs = PADS(out_data* : irq_n) ;
TIMEGRP fast_outs = PADS : EXCEPT : slow_outs ;
TIMESPEC TS08 = FROM : FFS : TO : fast_outs : 22 ;
TIMESPEC TS09 = FROM : FFS : TO : slow_outs : 75 ;

¿©·¯ºÐÀÌ FF to FF paths¿¡ ¿©·¯ °³ÀÇ cycle¸¦ °¡Áö°í ÀÖ´Ù¸é, TIMEGRP ¶Ç´Â TNM ¹®Àå Áß Çϳª¸¦ °¡Áö°í time group¸¦ ¸¸µé ¼ö ÀÖ½À´Ï´Ù.

ÁÖÀÇ»çÇ×: ¸¹Àº VHDL/Verilog synthesizers´Â flip-flop Q output net nameÀ» ¿¹»ó ÇÒ ¼ö°¡ ¾ø´Ù.  ±×·¯³ª, ´ëºÎºÐÀÇ synthesizer´Â flip-flop¿¡ ´ëÇÑ instance nameÀ» ¿¹»óÇÏ¿© ÇÒ´çÇÒ ¼ö ÀÖ´Ù.

TIMEGRP example:
TIMEGRP slowffs = FFS(inst_path/ff_q_output_net1* :
inst_path/ff_q_output_net2*);

TNM attached to instance example:
INST inst_path/ff_instance_name1_reg* TNM = slowffs ;
INST inst_path/ff_instance_name2_reg* TNM = slowffs ;

¸¸ÀÏ FF clock-enableÀÌ multi-cycle pathÀÇ ¸ðµç flip-flop¿¡ »ç¿ëÀÌ µÇ¸é, clock enable net¿¡ TNMÀ» ºÎÂøÇÒ ¼ö ÀÖ½À´Ï´Ù.  ÁÖÀÇ »çÇ× : forward trace ¹æ½ÄÀ¸·Î net¿¡ ºÎÂøµÈ TNMÀº net¿¡ ºÎÂøµÈ ¾î¶² FF, LATCH, RAM ¶Ç´Â PAD¿¡ Àû¿ë µÉ ¼ö ÀÖ½À´Ï´Ù.
NET ff_clock_enable_net TNM = slowffs ;

FROM:TO timespec¿¡ À־ "slowffs" timegroup¸¦ »ç¿ëÇÏ´Â ¿¹Á¦´Â À§¿¡¼­ º¸¿©ÁØ ¼¼°¡Áö ¹æ¹ýÁß ¾î´À Çϳª¸¦ °¡Áö°í ¸¸µç´Ù.
TIMESPEC TS10 = FROM : slowffs : TO : FFS : 100 ;

¾î¶² net¿¡ °ü·ÃµÈ delay ¶Ç´Â skew¸¦ Á¦ÇÑÇÑ´Ù.
NET any_net_name MAXSKEW = 7 ;
NET any_net_name MAXDELAY = 20 ns;

 

.ucf file¾È¿¡¼­ Á¦ÇÑ»çÇ×ÀÇ ¿ì¼±¼øÀ§´Â ´ÙÀ½°ú °°½À´Ï´Ù.

  1. Timing Ignore (TIG) -----> highest
  2. FROM : THRU : TO specs
  3. FROM : TO specs
  4. PERIOD specs -----> lowest

Ãß°¡ÀûÀÎ timespec Ư¡À̳ª ÀÚ¼¼ÇÑ Á¤º¸¸¦ ¾Ë°í ½ÍÀ»½Ã On-line "Library Reference Guide" document¸¦ º¸½Ã±æ ¹Ù¶ø´Ï´Ù.

 

LOCATION and ATTRIBUTE SPECIFICATIONS

 

Pin and CLB location locking constraints

 

Assign an IO pin number

INST io_buf_instance_name LOC = P110 ;
NET io_net_name LOC = P111 ;

 

Assign a signal to a range of I/O pins

NET "signal_name" LOC=P32, P33, P34;

 

Place a logic element(called a BEL) in a specific CLB location.
BEL = FF, LUT, RAM, etc...

INST instance_path/BEL_inst_name LOC = CLB_R17C36 ;

 

Place CLB in rectangular area from CLB R1C1 to CLB R5C7

INST /U1/U2/reg<0> LOC=clb_r1c1:clb_r5c7;

 

Place hierarchical logic block in rectangular area from CLB R1C1 to CLB R5C7

INST /U1* LOC=clb_r1c1:clb_r5c7;

 

Prohibit IO pin P26 or CLBR5C3 from being used:

CONFIG PROHIBIT = P26 ;
CONFIG PROHIBIT = CLB_R5C3 ;

Config Prohibit is very important for forcing the software to not use critical configuration pins like INIT or DOUT on the FPGA.  The Mode pins and JTAG Pins require a special pad so they will not be available to this constraint

 

Assign an OBUF to be FAST or SLOW:

INST obuf_instance_name FAST ;
INST obuf_instance_name SLOW ;

 

FPGAs only: IOB input Flip-flop delay specification

Declare an IOB input FF delay (default = MAXDELAY).
NOTE: MEDDELAY/NODELAY can be attached to a CLB FF that is pushed into an IOB by the "map -pr i" option.
INST input_ff_instance_name MEDDELAY ;
INST input_ff_instance_name NODELAY ;

 

Assign Global Clock Buffers Lower Left Right Side

INST gbuf1 LOC=SSW


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