Project proposal (< two pages) due May 9th

Outline for sample proposal:  gate sizing to minimize dynamic power


o Problem formulation
  * Given gate netlist and delay target
  * Find sizing for getes such that the delay is met and power is minimized

o Potential modeling
  * Delay:  elmore delay model
  * Power: dynamic power (proportional to size)

o Potential algorithm
  * Sensitivity based

o Experiment setting
  * MCNC benchmark
  * Compare sized circuit versus min-sized circuit

o Milestones
  * May 9 Problem formulation   
  * May 24 finish programming
  * May 30 initial results
  * June 6 algorithm improvement
  * June 11 final report