Group I:  floorplanning

o thermal aware floorplanning
Jue Wanf, Qun Gu, and Qiuyu Zhang

o Comparison of 3D and 2D CPU
Shane Erickson, Haru Yamamoto

o Floorplaning with RF interconnects
Joanna Ho

o Floorplaning with optical interconnects
Dan Vasquez and Jeffrey Wong

o uArch and floorplanning co-optimization for performance maximization
Luke Simonson

o placement optimizaiton of on-chip temperature sensors
Christopher Lucas, Pouya Dormiani, Steve Liu

Group II: circuit tuning

o transistor sizing with process variations
Cynthia and Phoebe

o simultaneous transistor sizing  and dual-vt assignment for
dynamic and sub-threshold leakage power reduction
Dan Lander and Wilber Duran

o simultaneous transistor sizing  and dual-tox assignment for
dynamic and gate leakage power reduction
Daniel Salce and Matthew Zobel


Group III: Emerging technologies

o physical design for low power FPGA 
David Omoto, David Lee, and Sabiha Hassan

o thermal and power modeling for net processor
Mehul Shah

o Mobile energy replenishment for fixed sensor nodes in a NIMS system
Jason Gordon, Steven Butt, Ryan Speelman