The following example shows how attributes can be used to make an 8-bit register
Specifications
Triggers on rising clock edge
Latches only on enable high
Has a data setup time of x_setup
Has propagation delay of pop_delay
ENTITY 8_bit_reg IS
GENERIC (x_setup, prop_delay, : TIME);
PORT (enable, clk : IN qsim_state;
a : IN qsim_state_vector (7 DOWNTO 0);
b : OUT qsim_state_vector (7 DOWNTO 0);
END 8_bit_reg;
qsim_state type is being used - includes logic values 0, 1, X, and Z
