 | Packages-- Notes Page -- |  |
| Packages-- Notes Page -- | |
A package contains a collection of user-defined declarations and
descriptions that a designer makes available to other VHDL entities.
Items within a package are made available to other VHDL entities
(including other packages) with a use clause. Some examples of
possible package contents are shown above.
The next two slides will describe the two parts of a VHDL
package, the package declaration and the package
body.