VHDL signal assignment statements can appear as either
sequential or concurrent statements. Outside of a
process, they are concurrent statements; inside a process they
are sequential statements. In either case, however, the assigned
signal will assume its new value after some determined delay (of
either some specified simulation time delay or one delta cycle)
The slide above provides two example. In the first example, assume
that the sensitivity list for the process does not list either
a or b (it could list some other signal, such as
swap_sig). In that case, a and b will swap
values one delta cycle after the process executes (essentially one
iteration of the type of loop seen in the example two slides before,
but the sensitivity list in this case prevents an endless cycle).
One important feature of sequential signal assignment statements
is illustrated in the second example above. Note that each process
only has one "driver" for each signal that have signal assignment
statements within the process. It is, therefore, possible to have
multiple assignment statements to the same signal within a process.
Note that multiple assignment statements to the same signal would not
be possible outside a process because they would then be concurrent
signal assignment statements with separate "drivers", and a Bus
Resolution Function" would be needed (Bus Resolution Functions will be
discussed in the 'Behavioral VHDL' module).
In the second example above, then, the two assignments to a are
executed sequentially. The first schedules a value of '1' to be
assigned to a one delta cycle in the future. The second
assignment statement then schedules a value of '0' also one delta
cycle in the future and will override the assignment from the first
statement because it was executed later. That is, the waveform
for a will be modified as a result of executing the second
signal assignment statement so that the assignment to take place
one delta cycle in the future will have a value '0' instead of '1'.
