Several examples are presented here to illustrate the subtleties of
sequential and concurrent execution. In the example on the left, the
two signal assignment statements will execute concurrently. The
resulting behavior of signals a and b will be the
perpetually swapping of their values in delta time. This behavior
results from each signal assignment causing a transition one delta
cycle in the future. When each signal is then updated, the signal
assignment statements will be evaluated again because each had a
transition in its "right-hand-side". Each signal will then be
assigned a new value seen in the subsequent delta cycle, and the cycle
continues endlessly.
In the example on the right, the variable assignments execute
sequentially because they are inside a process (the only place
VHDL variables can actually exist). The final value of both a
and b will be 0 since the first assignment will copy the
contents of b into a, and the second assignment will not
accomplish anything useful since b and a will have the
same value by then.
