Example Behavioral
VHDL Model

USE TEXTIO.all, mypackage.all;

ENTITY module is
  PORT (X, Y: in BIT; Z: out BIT_VECTOR(3 DOWNTO 0);
END module;

ARCHITECTURE behavior OF module is
  SIGNAL A, B: BIT_VECTOR(3 DOWNTO 0);
BEGIN
  A(0) <= X AFTER 20 ns; A(1) <= Y AFTER 40 ns
  PROCESS (A)
       VARIABLE P, Q: BIT_VECTOR(3 DOWNTO 0);
  BEGIN
       P := fft(A);
       B <= P AFTER 10 ns;
  END PROCESS;
  Z <= B;
END behavior;