Delay Types

There are several types of delay in VHDL, and understanding how delay works in a process is key to writing and understanding VHDL.

Simply put, any signal assignment in VHDL is actually a scheduling for a future value to be placed on that signal. When a signal assignment statement is executed, the signal maintains its original value until the time for the scheduled update to the new value. Any signal assignment statement will incur a delay of one of the three types listed in this slide.