The VHDL timing model drives the stimulus and response sequence of
digital hardware. At the start of a simulation, defined or implied
initial values are assigned to all signals. All processes not
suspended on wait conditions are executed concurrently until
they reach their respective wait statements; these process
executions will include signal assignment statements that assign new
signal values after prescribed delays. After signals assume their new
values, all processes examine their wait conditions to
determine if they can proceed. Processes that can proceed will then
execute concurrently until they all reach their respective wait
conditions. This cycle continues until the simulation termination
conditions are met or until all processes are suspended indefinitely
because no new signal assignments are scheduled to unsuspend any
process that is waiting.
