-- $Source: /evtfs/home/tres/vhdl/ref_design/RCS/sync_template.vhd,v $
-- $Revision: 1.3 $     $Date: 2006/04/06 21:14:28 $ 
-- Synthesis Template:
--              Overwrite the declarations and procedures with another design
-- Mike Treseler                         Mon Oct  3 09:51:23 2005
-------------------------------------------------------------------------------
-- See end of this file for the Process Template
-- See http://home.comcast.net/~mike_treseler/sync_template.vhd for this file.
-- See http://home.comcast.net/~mike_treseler/sync_template.pdf to see netlist
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity sync_template is
      generic (vec_len : positive := 8);
   port (
         clock : in  std_ulogic;
         reset : in  std_ulogic;
         a     : in  std_ulogic;
         q     : out std_logic_vector(vec_len-1 downto 0)      
         );

end entity sync_template;
-------------------------------------------------------------------------------
architecture synth of sync_template is     -- no signals required
begin
   sync_template : process(reset, clock) is
-------------------------------------------------------------------------------
-- Process declarations for the Template Procedures
-------------------------------------------------------------------------------
      subtype vec_t is unsigned(vec_len-1 downto 0);
      constant vec_init : vec_t := "10110011";
      variable    reg_v : vec_t ;
-------------------------------------------------------------------------------
-- Template Procedures: Always same three names. Contents varies.
-------------------------------------------------------------------------------
   procedure init_regs is       -- init of register variables only
      -- "regs" may end up as registers or wires (like verilog)
   begin
      reg_v := vec_init;
   end procedure init_regs;
-------------------------------------------------------------------------------
   procedure update_regs is     -- distilled functional description
   begin
      if a='1' then
         reg_v := rotate_left(reg_v,1);         
      end if;
   end procedure update_regs;   
--------------------------------------------------------------------------------
   procedure update_ports is -- wire register variables out to port
   begin
      q <= std_logic_vector(reg_v);
   end procedure update_ports;
   
-------------------------------------------------------------------------------
-- Process Template -- Always exactly the same:
-------------------------------------------------------------------------------
   begin  -- process template
      if reset = '1' then     -- Assumes synched trailing edge reset
         init_regs;           -- reg_v := init_c; No port init required
      elsif rising_edge(clock) then
         update_regs;         -- reg_v := f(reg_v); no port update need here
      end if;                 -- Synchronous init optional (state_v = idle_c)
      update_ports;           -- out_port <= reg_v;
   end process sync_template; -- will infer port wires ok for reset or clock
end architecture synth;
-------------------------------------------------------------------------------