-- $Source: /evtfs/home/tres/vhdl/play/RCS/proc_overload.vhd,v $
-- Revision  : $Revision: 1.12 $
-- $Date: 2007/09/17 19:49:21 $ 
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library ieee;
use ieee.std_logic_1164.all;
--                              Idea by Jonathan Bromley
package base_proc is
   signal clk_s : std_ulogic := '0';
   procedure tic;
   procedure set_bit (signal arg_s : inout std_ulogic);
end package;
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package body base_proc is
   procedure tic is
   begin
      wait until rising_edge(clk_s);
   end procedure;

   procedure set_bit (signal arg_s : inout std_ulogic) is
      -- packaged with signal args
   begin-- skip tic if already set
      if arg_s /= '1' then
         arg_s <= '1';
         tic;
      end if;
   end procedure set_bit;
end package body;
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library ieee;
use ieee.std_logic_1164.all;
use work.base_proc.all;

entity proc_overload is
end proc_overload;

architecture sim of proc_overload
is
   signal specific_signal_s : std_ulogic := '0';
begin
   clk_s <= not clk_s after 5 ns;

   main : process is
      -- overload packaged version for specific_signal_s
      procedure set_bit is
   begin-- 
      set_bit (specific_signal_s);  -- arg required here 
   end procedure set_bit;           -- but just once

   begin
      -- report "Test started.";
      assert clk_s = '0';
      assert specific_signal_s = '0'
         report "Error in proc_overload.";
      tic;                          -- see time 0
      set_bit;                      -- no arg required here
                                    -- use as often as needed
      assert specific_signal_s = '1'
         report "Error in proc_overload.";
      report "Test complete. No assertions expected above";
      wait;
   end process main;
end sim;
-- Sample session:
-- 68 Wed Apr 11 /evtfs/home/tres/vhdl/play>
-- vsim -c proc_overload
--VSIM 7> run 20 ns
--# ** Note: Test complete. No assertions expected above
--#    Time: 15 ns  Iteration: 0  Instance: /proc_overload
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