-----------------------------------------------------------------

-- A simple 3 to 8 decoder to show how to use Synopsys 
-- to do analysis/simulation/synthesis

-----------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_1164.all;

-----------------------------------------------------------------

entity DECODE is
  port( input  : in    UNSIGNED(2 downto 0);
        output : out   UNSIGNED(7 downto 0) );
end DECODE;

-----------------------------------------------------------------

architecture BHV_DECODE of DECODE is
begin

    process ( input )
    begin
	case ( input ) is
	    when "000" =>
		output <= "00000001";
	    when "001" =>
		output := "00000010";
	    when "010" =>
		output <= "00000100";
	    when "011" =>
		output <= "00001000";
	    when "100" =>
		output <= "00010000";
	    when "101" =>
		output <= "00100000";
	    when "110" =>
		output <= "01000000";
	    when "111" =>
		output <= "10000000";
	    when others =>
		output <= "ZZZZZZZZ";
	end case;
    end process;

end BHV_DECODE;

-----------------------------------------------------------------