GATEWAY LABORATORY: SESSION THREE

Objectives

  1. to undertake a small system design
  2. to write-up such a design for publication ;-)

Initial Example

Take a good look at the THE UNIVERSAL ASYNCHRONOUS RECEIVER Make sure you understand the problem, and then what each module does. This is an exercise in in understanding both a specification and existing code - aim to spend about an hour of concentrated activity on this.

Once you have a grasp of the structure, consider how to modulfy the receiver with a final parity bit (after the 8th bit of data and before the stop bit). A parity bit is set HIGH if there are an odd number of 1s in the data, and zero if there are an even number. The receiver should calculate the appropriate value of the parity bit for the data received, compare this with the parity bit received and set the Framing error output if the results disagree (as well as if the stop_bit is LOW).

Second Example

A complete example from the 1996-7 design class can be found at the Gateway home page .

Design Exercise : the Median Filter

The exercise is based upon a past paper in the European Solid-State Circuits Conference of 1991. This is a realistic approach in that you might be working for a company which needs a median filter and your boss might have found this paper and simply given it to you to implement.

Your job is to understand the specification and to implement a gate-level design which finds the the median value over five 4-bit numbers.

Your task is partially done for you in that a senior design engineer has already created a behavioural model which was used in designing a larger system. Read it carefully so that you understand it. Using this as your test bench, you can proceed to design the gate-level version.

In attempting this design notice two things:

  1. The value stored in each cell is an m-bit word (where m is the width of the data being ordered) and so requires m dtypes or a behavioural model of an m-bit dtype.
  2. To initialise the entire array (so that the assumption of ordered data is valid) a reset signal must be included in the design of the dtypes.

You are expected to produce a design with the details of the gate-level implementation down to primitive boolean gates and a dtype (or an m-bit dtype) which, of course, will be behavioural.

It is strongly recommended that you:

  1. produce a behavioural module for the symbol in figure 2
  2. produce a module which calls instances to implement figure 1 (be careful as to the value of the ND input to the right-most block)
  3. test it in comparison to the behavioural module of the whole filter
  4. when that is working, replace the figure 2 module with a gate-level equivalent.

This design should be written-up as an Electronics Letter as explained in the Gateway home page .