GATEWAY LABORATORY: SESSION TWO

Objectives

The objectives of this session are:

• to check your understanding of session one
• to look at timing issues in circuit design and Verilog encoding

Answers to session ONE exercises

It will be far better if you complete session two before attempting session three. However, once this is done (or when life gets too tough) the answers to the first two activities are given below:

• Activity 1: 1, 2 ( 2 - but poor), 3, 4, 5, 6, 7, and 8.
• Activity 2: 1&2, and 3&4.

Tutorial on Delays

Go to the following tutorial and work your way through it.