Comments on “bad” Priority Circuit
This is a bad attempt by a neophyte VHDL writer at a priority circuit. There are multiple things wrong with this description.
There are multiple concurrent statments driving the DOUT signal. This means MULTIPLE GATE output are tied to dout signal! Physically, this will create an unknown logic condition on the bus.
The writer seems to think that the order of the concurrent statements makes a difference (ie, the last concurrent statement just assigns a '000'). The order in which you arrange concurrent statements MAKES NO DIFFERENCE. The synthesized logic will be the same.
- Ordering of statements only makes a difference within a process. This is why statements within a process are called 'sequential' statements; the logic synthesized reflects the statement ordering (only for assignments to the same output).