Comments on ‘bad’ architecture
In the above process, the ELSE clause was left out. If the 'if' statement condition is false, then the output Y is not assigned a value.
- In synthesis terms, this means the output Y should have a LATCH placed on it!
- The synthesized logic will have a latch placed on the Y output; once Y goes to a '1', it can NEVER return to a '0'!!!!!
This is probably the #1 student mistake in writing processes. To avoid this problem do one of the following things:
- ALL signal outputs of the process should have DEFAULT assignments right at the beginning of the process (this is my preferred method, is easiest).
- OR, all 'if' statements that affect a signal must have ELSE clauses that assign the signal a value if the 'if' test is false.