library ieee;
use ieee.std_logic_1164.all;

-- 8 Bit Register, synchronous load, asynch reset
entity reg8 is
  port (  clk,reset:  in std_logic;
	  sload: in std_logic;
	  din   : in std_logic_vector(7 downto 0);
	  dout  : out std_logic_vector(7 downto 0)
   );
end reg8;

architecture a of reg8 is
        
   signal  reg_state: std_logic_vector(7 downto 0);

begin

  dout <= reg_state;

   stateff:process(clk)
     begin
     if (reset = '1') then
        -- asynchronous reset
        reg_state <= "00000000";
     elsif (clk'event and clk='1') then  
       -- synchronous load
       if (sload = '1') then
          reg_state <= din;
       end if;
     end if;
    end process stateff;

end;