-- vhdl model for 8 level priority circuit
--*************************************************************************
-- IO Interface Declaration
--*************************************************************************

library ieee;
use ieee.std_logic_1164.all;

entity priority is
port
(
-- inputs
  signal    y1:  in  std_logic;  
  signal    y2:  in  std_logic;  
  signal    y3:  in  std_logic;  
  signal    y4:  in  std_logic;  
  signal    y5:  in  std_logic;  
  signal    y6:  in  std_logic;  
  signal    y7:  in  std_logic;  

-- outputs
  signal vec:  out std_logic_vector(2 downto 0)      
);
end priority;

--*************************************************************************
-- Architecture body
--*************************************************************************

architecture behavior of priority is
begin
  process (y1,y2,y3,y4,y5,y6,y7)
  begin

	if (y7 = '1') then vec <= "111";
        elsif (y6 = '1') then vec <= "110";
        elsif (y5 = '1') then vec <= "101";
        elsif (y4 = '1') then vec <= "100";
        elsif (y3 = '1') then vec <= "011";
        elsif (y2 = '1') then vec <= "010";
        elsif (y1 = '1') then vec <= "001";
	else vec <= "000";
	end if;

  end process;

end behavior;