library ieee;
use ieee.std_logic_1164.all;
-- 3 input majority function using a process 
entity newmajor is
    port (   A, B, C :  in std_logic;
                  Y:   out std_logic
         );
end newmajor;

ARCHITECTURE a of newmajor is

 begin

    process (A, B, C)
      
     begin
        Y <= '0';
        if ((A= '1') and (B = '1')) then
           Y <= '1';
        end if;

        if ((A='1') and  (C = '1')) then
           Y <= '1';
        end if;
 	
        if ((B = '1') and (C = '1')) then
            Y <= '1';
        end if;

     end process;
end a;