library ieee;
use ieee.std_logic_1164.all;

-- 4 to 1 mux, 8 bit inputs, using sequential statement

entity muxbad is
  port (  
	  I0,I1,I2,I3   : in std_logic_vector(7 downto 0);
	  sel : in std_logic_vector(1 downto 0);
	  dout : out std_logic_vector(7 downto 0)
   );
end muxbad;

architecture a of muxbad is
        
begin

 process (sel,I0, I1, I2, I3)
   begin
     
     if (sel = "00") then
        dout <= I0;
     elsif (sel = "01") then
        dout <= I1;
     elsif (sel = "10") then
        dout <= I2;
     else
        dout <= I3;
     end if;

   end process;

end a;