library ieee;
use ieee.std_logic_1164.all;

-- 4 to 1 mux, 8 bit inputs, using concurrent statements

entity mux4to1_8_conc is
  port (  
	  I0,I1,I2,I3   : in std_logic_vector(7 downto 0);
	  sel : in std_logic_vector(1 downto 0);
	  dout : out std_logic_vector(7 downto 0)
   );
end mux4to1_8_conc;

architecture a of mux4to1_8_conc is
        
begin

 WITH sel SELECT
   dout <= I0 when "00",
           I1 when "01",
           I2 when "10",
           I3 when others;

end a;