library ieee;
use ieee.std_logic_1164.all;

entity  moore is
 port (a,clk, reset: in std_logic;
        z: out std_logic);
end moore;


architecture a of moore is

  signal state: std_logic_vector(1 downto 0);

  -- explicit state assignments
  constant S0: std_logic_vector(1 downto 0) := "00";
  constant S1: std_logic_vector(1 downto 0) := "01";
  constant S2: std_logic_vector(1 downto 0) := "10";
  constant S3: std_logic_vector(1 downto 0) := "11";

begin

  -- process for the state bits of the machine
  process  (clk)
   begin

     if (reset = '1') then
       -- explicit async reset
       state <= S0;
     elsif (clk'event and clk = '1') then  -- rising edge

       case  state is
	 when S0 => 
	   Z <= '1';
           if ( a = '1') then state <= S2; end if;
	 when S1 => 
	   Z <= '0';
           if ( a = '1') then state <= S3; end if;
	 when S2 => 
	   Z <= '0';
           if ( a = '1') then state <= S3;
	    else  state <= S1; end if;
	 when S3 => 
	   Z <= '1';
           if ( a = '1') then state <= S0; end if;
	 when OTHERS =>
	   Z <= '0';
       end case;
    end if;
  end process;


end a;