library ieee;
use ieee.std_logic_1164.all;

entity  mealy is
 port (a,clk, reset: in std_logic;
        z: out std_logic);
end mealy;


architecture a of mealy is

  signal nstate,pstate: std_logic_vector(1 downto 0);

  -- explicit state assignments
  constant S0: std_logic_vector(1 downto 0) := "00";
  constant S1: std_logic_vector(1 downto 0) := "01";
  constant S2: std_logic_vector(1 downto 0) := "10";
  constant S3: std_logic_vector(1 downto 0) := "11";

begin

  -- process for the state bits of the machine
  seq:process (clk)
   begin

     if (reset = '1') then
       -- explicit async reset
       pstate <= S0;
     elsif (clk'event and clk = '1') then  -- rising edge
        pstate <= nstate;
     end if;

  end process seq;

  comb:process (a,clk)
   begin

       -- default assignments
       nstate <= pstate;
       Z <= '0';

       case  pstate is
	 when S0 => 
	   Z <= '1';
           if ( a = '1') then nstate <= S2; end if;
	 when S1 => 
           if ( a = '1') then nstate <= S3; end if;
	 when S2 => 
           if ( a = '1') then nstate <= S3;
	    else  nstate <= S1; end if;
	 when S3 => 
	   Z <= '1';
           if ( a = '1') then nstate <= S0; end if;
	 when OTHERS =>
	   Z <= '0';
       end case;

  end process comb;


end a;