library ieee;
use ieee.std_logic_1164.all;

entity dffr8 is
  port (  din:  in std_logic_vector(7 downto 0);
	  clk:  in std_logic;
	  aclr:  in std_logic;  
	  dout: out std_logic_vector(7 downto 0)
       );
 end dffr8;

 architecture a of dffr8 is
 begin

	main:process(clk,aclr)
	begin
	  if (aclr = '1') then
	    -- asynchronous reset
	    dout <= (others => '0');
	  elsif (clk'event and clk='1') then  
	  -- rising edge of clock
	  dout <= din;
          end if;
        end process main;
 end a;