-- vhdl model for the 3 to 8 decoder

--*************************************************************************
-- IO Interface Declaration
--*************************************************************************

library ieee;
use ieee.std_logic_1164.all;

entity dec3to8 is
port
(
-- inputs
  signal    sel:  in  std_logic_vector(2 downto 0);  -- selector
  signal    en:  in  std_logic;                  -- enable

-- outputs
  signal y:  out std_logic_vector(7 downto 0)       -- outputs are low true
);
end dec3to8;

--*************************************************************************
-- Architecture body
--*************************************************************************

architecture behavior of dec3to8 is
begin
  process (sel,en)
  begin
 
    y <= "11111111";
    if (en = '1') then 
	case sel is
	 when "000" => y(0) <= '0';
         when "001" => y(1) <= '0';
         when "010" => y(2) <= '0';
         when "011" => y(3) <= '0';
         when "100" => y(4) <= '0';
         when "101" => y(5) <= '0';
         when "110" => y(6) <= '0';
         when "111" => y(7) <= '0';
	 when others =>  y(7) <= '0';
       end case;
    end if;
  end process;
end behavior;