library ieee;
use ieee.std_logic_1164.all;

entity  dec2x4 is
 port (a,b,enable: in std_logic;
        z: out std_logic_vector( 3 downto 0)
	);
end dec2x4;
     
architecture DEC_CONC  of dec2x4 is

begin

  z(0) <= '1' when ((enable='1') and (a='0') and (b='0'))  else '0';
  z(1) <= '1' when ((enable='1') and (a='0') and (b='1'))  else '0';
  z(2) <= '1' when ((enable='1') and (a='1') and (b='0'))  else '0';
  z(3) <= '1' when ((enable='1') and (a='1') and (b='1'))  else '0';

end DEC_CONC;