library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- 4 Bit Counter
entity cnt4 is
  port (  clk,reset:  in std_logic;
	  cnt_en,sload: in std_logic;
	  din   : in std_logic_vector(3 downto 0);
	  dout  : out std_logic_vector(3 downto 0)
   );
end cnt4;

architecture a of cnt4 is
        
   signal  cnt_state: std_logic_vector(3 downto 0);

begin

  dout <= cnt_state;

   stateff:process(clk)
     begin
     if (reset = '1') then
        -- asynchronous reset
        cnt_state <= "0000";
     elsif (clk'event and clk='1') then  
       if (cnt_en = '1') then
         cnt_state <= cnt_state + 1;
       end if;
       -- sload takes precedence over counting
       if (sload = '1') then
          cnt_state <= din;
       end if;
     end if;
    end process stateff;

end;