library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- 8 Bit Unsigned Comparator with outputs registered 
-- for pipelining

entity cmp8_reg is
  port (  clk:  in std_logic;
	  A,B   : in std_logic_vector(7 downto 0);
	  aeqb, altb, agtb  : out std_logic
   );
end cmp8_reg;

architecture a of cmp8_reg is
        
begin

-- process that has combinational logic with DFFs on output for latching outputs
process

 begin
  wait until clk'event and clk='1';
   if (a = b) then aeqb <= '1'; 
    else aeqb <=  '0'; end if;

  if (a < b) then altb <= '1';
   else altb <= '0'; end if;

  if (a > b) then agtb <= '1';
   else agtb <= '0'; end if;

end process;

end a;