library ieee;
use ieee.std_logic_1164.all;

entity adder4 is

port (
 signal a,b: in std_logic_vector (3 downto 0);
 signal cin: in std_logic;
 signal sum: out std_logic_vector(3 downto 0);
 signal cout: out std_logic
);
 end adder4;

architecture behavior of adder4 is

 signal c: std_logic_vector(4 downto 0);
 begin

    process (a,b,cin,c)
    begin
     c(0) <= cin;
       
     for i in a'range loop

      sum(i) <= a(i) xor b(i) xor c(i);
      c(i+1) <= (a(i) and b(i)) or 
	      (c(i) and (a(i) or b(i)));
     end loop;

     cout <= c(c'HIGH);

 
 end process;

 end behavior;