library ieee;
use ieee.std_logic_1164.all;

-- FSM for pattern matching
entity ramfsm is
  port (  clk:  in std_logic;
	  reset: in std_logic;
	-- control inputs
	  zero:  in std_logic;
	  cnt_eq: in std_logic;

	-- control ouputs
	
	  set_busy:  out std_logic;
	  clr_busy:  out std_logic;
      addr_sel: out std_logic;
      cnt_en:  out std_logic;
      ld_cnt:  out std_logic;
	  zero_we: out std_logic;

 	  state: out std_logic_vector(1 downto 0)
   );

end ramfsm;


architecture a of ramfsm is

  signal nstate,pstate: std_logic_vector(1 downto 0);

  CONSTANT S0 : std_logic_vector(1 downto 0) := "00";
  CONSTANT S1 : std_logic_vector(1 downto 0) := "01";
  CONSTANT S2 : std_logic_vector(1 downto 0) := "10";

 begin

   state <= pstate;

   stateff:process(clk)
     begin
	  if (reset = '1') then
        pstate <= S0;
      elsif (clk'event and clk='1') then  
	  -- rising edge of clock
	    pstate <= nstate;
       end if;
    end process stateff;
   	  
   comb: process(pstate, zero, cnt_eq ) 
     begin
	
      -- default outputs
	  set_busy <= '0';
	  clr_busy <= '0';
      addr_sel <= '0';
      cnt_en <= '0';        
      ld_cnt <= '0';
	  zero_we <= '0';

	
       CASE pstate IS
       	WHEN S0 =>
       	    if (zero = '1') then
	          nstate <= S1;
            else
             nstate <= S0;
	        end if;
	    WHEN S1 =>
	      set_busy <= '1';  
	      ld_cnt <= '1';  -- load counter with 'low' value
                           -- get ready to write
	       nstate <= S2;
       
        WHEN S2 =>
	       addr_sel <= '1';  -- want address from Counter
	        zero_we <= '1';   -- want WE to go high
	        cnt_en <= '1';    -- need to increment address
	      if (cnt_eq = '1') then
	          clr_busy <= '1';	-- at last address
              nstate <= S0 ;
	       else
              nstate <= S2;
	       end if;
	     WHEN others =>
             nstate <= S0;

       end case;
     end process comb;
 end a;