library ieee;
use ieee.std_logic_1164.all;

-- FSM for pattern matching
entity ramfsm is
  port (  clk:  in std_logic;
	  reset: in std_logic;
	-- control inputs
	  zero:  in std_logic;
	  cnt_eq: in std_logic;

	-- control ouputs
	
	  set_busy:  out std_logic;
	  clr_busy:  out std_logic;
      addr_sel: out std_logic;
      cnt_en:  out std_logic;
      ld_cnt:  out std_logic;
	  zero_we: out std_logic;

 	  state: out std_logic_vector(1 downto 0)
   );

end ramfsm;


-- Recommended FSM code if using Student Edition Version 7.21
architecture a of ramfsm is

  signal pstate: std_logic_vector(1 downto 0);

  CONSTANT S0 : std_logic_vector(1 downto 0) := "00";
  CONSTANT S1 : std_logic_vector(1 downto 0) := "01";
  CONSTANT S2 : std_logic_vector(1 downto 0) := "10";

 begin

   state <= pstate;

   stateff:process(clk)
     begin
      if (reset = '1') then
        pstate <= S0;
      elsif (clk'event and clk='1') then  
	  -- rising edge of clock
       CASE pstate IS
       	WHEN S0 =>
       	    if (zero = '1') then
	          pstate <= S1;
	    end if;
	WHEN S1 =>
	    pstate <= S2;
        WHEN S2 =>
	      if (cnt_eq = '1') then
               pstate <= S0 ;
              end if;
	WHEN others =>
            pstate <= S0;
       end case;

     end if;
    end process stateff;

   set_busy <= '1' when (pstate  = S1) else '0';
   ld_cnt <= '1' when (pstate = S1) else '0';
   addr_sel <= '1' when (pstate = S2) else '0';   
   zero_we <= '1' when (pstate = S2) else '0';   
   cnt_en <= '1' when (pstate = S2) else '0';   
   clr_busy <= '1' when (pstate = S2 and cnt_eq = '1') else '0';   

 end a;