library ieee;
use ieee.std_logic_1164.all;

-- 6 bit register
entity reg6 is
  port (  clk:  in std_logic;
	  reset: in std_logic; -- async reset
	  ld: in std_logic;    -- synchronous load
	  din: in std_logic_vector(5 downto 0);
	-- outputs
	  dout: out std_logic_vector(5 downto 0)
       );
 end reg6;

architecture a of reg6 is
 begin
   main:process(clk)
     begin
      if (reset = '1') then
	     dout <= "000000";
      elsif (clk'event and clk='1') then  
	  -- rising edge of clock
	     if (ld = '1') then
	      dout <= din;
	      end if;
       end if;
     end process main;
 end a;