Objective:                

The objective of this lab is to introduce the student to writing VHDL that describes a sequential system. This lab is worth 100 pts.

To Do:

The VHDL entity shown below:

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

 entity updnshift8 is

-- precedence of synchronous control (highest to lowest)
-- sclr -> ld - > func
--
port (
signal din: in std_logic_vector (7 downto 0); -- data for parallel load
signal clk: in std_logic;
signal aclr: in std_logic; -- asynchronous clear
signal sclr: in std_logic; -- synchronous clear
signal ld: in std_logic; -- when high, load counter with DIN
signal down: in std_logic; -- if counting: if '1' count down, else count up
signal sleft: in std_logic; -- if shifting: if '1' shift left, else shift right
signal func: in std_logic_vector(1 downto 0); -- enable counting/shifting
signal sin: in std_logic; -- shift 'in' bit
signal dout: out std_logic_vector(7 downto 0)
);
end updnshift8;

defines a register that has up/down counting, parallel load, and right/left shifting capabilities.

The function of the register is as follows:

a.  sclr is a synchronous clear that has highest precedence

b.   ld is a load line that will load the register contents from the din bus. The load function has a lower precedence than the synchronous clear function.

c.  The two bit func input controls the counting/shifting functions. If func="00", then no counting or shifting is done. If func = "01", then count by 1, where the count direction is determined the "down" control line. If func = "10", then shift by 1, where the shift direction is determined by the 'sleft' control line and the shift bit by the 'sin' data bit.  If func is "11", then the register value is both counted and shifted (in the same clock, count is first).

Implementation Guidelines                                                

You are to write the architecture that implements the functionality defined above.   To do a increment or decrement, you can simply use the '+' addtion, subtraction operator as follows:

       a <=  a + 1;

or

      a <= a - 1;

where 'a' is a signal of std_logic_vector types.  If you use a variable instead of a signal, then the '<=' operator is replaced by ':='. . It is important that you include the statements:

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

at the top of the file; this directs the synthesis tool how to generate an adder for a std_logic type.

You should not try to do everything in the first pass --- first get the SCLR, ACLR, LOAD functions working.  Then do the up/down counting function,  followed by the shifting function, and fnally the combined count + shift function.  Look at the test waveform mentioned in the next section and be sure you understand the function of each control line.

Testing Your Design                                              

The CSGOLD.SCF file below is a golden waveform file.   Save it as "updnshift8.scf" and then compare your results against the golden results.

RIGHT CLICK on each filename to save to disk:     CSGOLD.SCF

To Turn In

A code listing of your VHDL file.

Check Off                                                      

You must DEMONSTRATE you updnshift8 design to the TA and show that your results matches the expected results.