library ieee;
use ieee.std_logic_1164.all;

-- FSM for testing Student Version Bug
entity fsmgood is
  port (  clk:  in std_logic;
	  reset: in std_logic;
	  in_a: in std_logic;
	  in_b: in std_logic;
	  in_c: in std_logic;
	-- outputs
	  state: out std_logic_vector(2 downto 0)
       );
 end fsmgood;

architecture a of fsmgood is

  signal nstate,pstate: std_logic_vector(2 downto 0);
  
  CONSTANT S0 : std_logic_vector(2 downto 0) := "000";
  CONSTANT S1 : std_logic_vector(2 downto 0) := "001";
  CONSTANT S2 : std_logic_vector(2 downto 0) := "010";
  CONSTANT S3 : std_logic_vector(2 downto 0) := "011";
  CONSTANT S4 : std_logic_vector(2 downto 0) := "100";

 begin

   state <= pstate;

   stateff:process(clk)
     begin
      if (reset = '1') then
	     pstate <= S0;
      elsif (clk'event and clk='1') then  
	  -- rising edge of clock
	    pstate <= nstate;
      end if;
     end process stateff;

   comb: process (pstate, in_a, in_b, in_c) 
     begin
       ---nstate <= pstate;  -- this default assignment causes
	                      -- incorrect logic to be synthesized in student
	                      -- version.
       -- instead of using default assignment, add explicit 'else' clauses	
       -- to indicate if we need to remain in same state
       CASE pstate IS
       	WHEN S0 =>
	    if (in_a = '1') then nstate <= S1; 
	    else  nstate <= S0; end if;
       	WHEN S1 =>
            nstate <= S2;
        WHEN S2 =>
	      if (in_b = '1') then nstate <= S3; 
	       else  nstate <= S2;  end if;
        when S3 =>
	       if (in_c = '1') then nstate <= S4;	
	        else nstate <= S3;  end if;
	    when S4 =>
	       if (in_b = '1') then nstate <= S3; 
	        else nstate <= S4;  end if;
       	WHEN OTHERS =>
	       nstate <= S0;
       END CASE;
     end process comb;
   
 end a;