EE 4743/6743
Computer Aided Design of Digital Systems
Class Policy and Syllabus (Spring '03)

Bob Reese
Simrall 335 , 325-3154

ECE office, MWF 2:30-4:00 – it is a good idea to always call first in case I have been dragged into a meeting.
Email address: reese@ece.msstate.edu

WWW Page: http://www.ece.msstate.edu/~reese/EE4743

Textbooks:
1. Course Notes – I will try to place all notes online.
2. Fundamentals of Digital Logic with VHDL Design, Stephen Brown and Zvonko Vranesic, Mc-Graw-Hill, 2000, ISBN 0-07-235596-4.
3. The entire WWW J .

Grade Determination:
(3) Exams 50%
(1) Final 20%
Labs/HW 30%
____
100%

Grade assignment is on a 10-point scale.

In addition to the percentage distributions above, you must achieve at least a 60% grade average on ALL in-class material (exams + final) and a 60% grade average on all out of class material (labs+homework) in order to get a ‘D’ in the course. This prevents you from simply ignoring either the in-class material or out-of-class material in favor of the other.

The workstation lab on the first floor of Simrall is considered an OPEN lab. This means you can work on your assignment anytime the lab is open and you can find a free machine. Your assigned lab period is a time in which you will be GUARANTEED a machine; you should go to the lab during your assigned lab period because the instructor will be available for questions and help. Typically, a lab will be due 1 to 2 weeks after it is handed out. You should start on the lab IMMEDIATELY since the assignment will generally take longer than the assigned lab period and competition for the lab machines will become fierce as the due date draws near. It will not be unusual for a new lab assignment to overlap a previous lab assignment. I do not assign homework in this class because of the amount of work required on the lab assignments. Doing a good job on the lab assignments directly affects your test grade because test questions are related to work done in the lab.

ACADEMIC DISHONESTY

Occasionally, we have a problem in this course with Academic Dishonesty. Academic Dishonesty is when you present some other person's work as your own. The following is my definition of academic dishonesty:

• Looking at or copying any material from another student. This material could be schematics, VHDL files, simulation files, etc. The person providing this material would also be guilty of academic dishonesty.

You may DISCUSS external homeworks, and verbally answer questions about homeworks from other students. You may not SHOW your homework to another student, or provide an 'old copy' as an example!!!!

If I find a student guilty of academic dishonesty, expect an F in the course and an academic dishonesty claim to go into your permanent academic record.

COURSE SOFTWARE

We will be using the Altera Maxplus software package which is contained on a CDROM in the back of your Textbook. This same software is available on the Unix workstations.

Syllabus (this is approximate schedule and it can be changed!!!)

Course Topics and Order of Coverage

Week 1 (Jan 6) : Combinational, Sequential Logic Review, Maxplus Overview, Lab #0 (MWF meet)

Week 2 (Jan 13) : VHDL Comb Logic, Fixed Point discussion, Combinational Logic (Lab #0 due),Lab #1 - Intro to Maxplus, MWF meeting,

Week 3 (Jan 20) : Lab #1 due, WF meeting, Fixed Point, System Timing discussions, Lab #2 discussion (Saturating adder). Monday is a holiday, Monday labs need to attend another section, or do lab on home PCs.

Week 4 (Jan 27): MWF Meeting: Introduction to Pipelining, Implementation Technologies, Discuss Lab #3 - Altera LPMs (Lab #2 due)

Week 5 (Feb 3) : FPGA Families, Sequential Systems in VHDL, Discuss Lab #4 Timing, Pipelining (Lab #3 due). Test #1 on Wednesday (MW Meeting).

Week 6 (Feb 10) FSMs in VHDL, Ram Zero Dpath example, Discuss Lab #5 - (Lab #4 due)

Week 7 (Feb 17): Scheduling, Data Flowgraphs, Discuss Lab #6 Bilinear Filtering, Part 1, Lab #5 due.

Week 8 (Feb 24) : In Class Group Assignments, Discuss Lab #6 Bilinear Filtering, Part 2, Progress checkoff of Part #1.

Week 9 (Mar 3): Altera FPGA Architecture, Xilinx/Actel FPGA Arch, Discuss Lab #6, Bilinear Filtering, Part #3. (Complete checkoff of Lab #6, Part #1)

Mar 10 – SPRING BREAK!!! YAHOO!!!!

Week 10 (Mar 17): Altera Stratix Architecture, Discussion of Serial IO, Test #2 on Friday. Lab #7 Discussion. Complete Checkoff of Lab #6, Part #2.

Week 11 (Mar 24) : Structural VHDL, Checkoff of Lab #6, Part #3. Lab #7 Part #1 Assigned

Week 12 (Mar 31): Design for Test, Lab #7, Part #2, Assigned (Lab #7, Part #1 due)

Week 13 (Apr 7): Video Displays, Lab #8 Structural VHDL implementation of previous lab (Lab #7, Part #2 due). Monday only meeting.

Week 14 (Apr 14) Verilog Introduction, Lab #8 Due. Monday only meeting.

Week 15 (Apr 21) : No Lab meetings. Monday only, Test #3.

Week 16 (Apr 28) : No Lab Meetings. Monday only, Review for Final..