IEEE Timing Working Group
Minutes - June 19, 1993

The IEEE Timing Working Group met following the DAC at a facility
provided by TI in the Dallas area. Special thanks to Steve Schulz
for arranging this convenient meeting site and to TI for providing
the facility.

The attendees were:
Steve Schulz TI
Ian Green Genrad
Mark O'Driscoll Genrad
Jacques Rouillard LEDA
Jim St. Pierre IBM
David Bernstein Vantage
Jorge Seidel Intergraph
Alfred S. Gilman Intermetrics
Oz Levia Synopsys
Maruius Lan Lier Philips
Ton de Jager Philips
John Hillawi DASL
Graham Davies Viewlogic
Mitchell Perilstein Compass
Daniel Barclay Compass
Gar Kuey Cheng NAWCAD
Clive Charlwood Synopsys
Michael Haney U of Illinois
Andrew Guyler Mentor Graphics
Murali Bharathala Ikos
Ken Simone SEE, Inc.
Lou Concha Wright Lab.
Mark Hamilton RACAL-REDAC
Peter Barck MITRE
Bill Paulsen Viewlogic
Masaharu Imai TUT, Japan
Venkat Venkataraman IBM
Joseph Flanigan IBM

The meeting began with introductory remarks and presentation of the
agenda by the chairmain.
1. The PAR for this group was approved by NESCOM and the
PAR number 1076.4 was assigned. T
2. The main agenda item for the meeting was the discussion
of the VITAL 2.0 Model Development Specification and
how it would evolve into the standard being developed
by this WG.

VITAL Status

The VITAL 2.0 Model Development Spec had been reviewed by
a large industry group in May at a meeting held at Synopsys. The
result of this review meeting was a suggested set of changes/update
to the spec. During the period between the May meeting and this
meeting, Bill Billowitch (Technical Director of VITAL) had been
working on updating the Spec based on these inputs and action items
identified at the May meeting. While the new spec had not been
completed, enough work had been done to be presented and reviewed
by the WG. This technical presentation and review occupied the
rest of the meeting.

Issues Raised

1.A question about the limitations/definition of negative SETUP/HOLD
times was raised. This was clarified and an action to reword the
spec was taken by WDB.
2.The evolution of the with respect to Generic Parameters was
explained
- Initial EDA feedback indicated that proliferatin of generics
would have negative impact on simulation performance
- The concept of encapsulating the generics in an separate
package containing an array of values was developed and put
forward in the 2.0 VITAL spec (the Tval Pkge).
- This idea was rejected by the May meeting based on perceived
problems with configuration management of the separate data
packages and the general feeling that performance issues
with generics were no longer a substantivie problems due
to improvements in VHDL simulators.
- The updated spec relies on generics to represent delay place
holders and provides a mapping from the SDF names to those
generic parameters.

3.Classes of Generic Parameters

SDF provides a means to represent sets of delays to cover cases
where delays are provided for cobinations of state transitions. These
range from single values where delays are the same for all transitions
to groups of 12 delays where a separate value is given for all
combinations of 0,1,X,Z. A proposal to assign a different type
for each of these was made and discussed. The consensus of the
group was that this would be to restrictive and that delay
information should be aggregates of the same type.

4.Min/Max Support

Since the spec only proposes supporting the selection of a single
element of (min,typ,max) timing (i.e. only a single set of data for
a simulation) how will Min/Max simulation be supported? Suggestion:
Provide a different timing type that provides more complex data, e.g.
a record structure.

5. Since either arrays or records can be used to hold groups of generics
which is better? After some discussion of performance, flexibility, and
data typing the group concluded that arrays were a better solution.

6.It was suggested that the requirment for "path name string" in functions
was no longer needed (because of VHDL92 features) and should be removed.

7.Prmitives: It was decided to include specific primitives for 2,3,4
inputs (for logical funcitons where this makes sense) as well as
generically sized primitives. The group felt that this would improve
performance.

8.Compliance: Primitives will be part of the specification but compliance
will not imply using only these primitives. Thus the expectation is that
EDA vendors will optimize these primitives but more general modeling
will be allowed.

9.Reference to VHDL87: The current timing spec will reference VHDL 87
but the issue of VHDL 92 support will be re-visited ASAP. Of particular
importance is the support of extended identifiers and extended character
set.

10.Truth/State Tables: The proposed solution for truth/state table
representation should be broadened to support multiple outputs.

11.SDF Control: Ownership of the SDF spec should be clarified so that
references are made to an IEEE contolled document.

Action/Plans

Based on the input at this meeting the VITAL Spec will be revised and
distributed for review by the end of July. Following this review
period, an in-depth design review will be scheduled (August/Sept) to
finalize a draft specification for standardization.

Sincerely,
Victor Berman
chairman, IEEE Timing WG
berman@cadence.com
508-446 6276