--
-- Rcsid[] = "$Id: intrupt1.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

-- This module consists of the MASK registers, TRAP flipflop, RST 7.5
-- flipflop, and INTE flipflop(with associated control logic).
-- It also contains the priority encoder as a component.

entity intrupt1 is
port(
    PRIENCODE: out bit_vector(2 downto 0);
    EI,MASK75SET,MASK65SET,MASK55SET,RST75SET: out bit;
    TRAP,RST75,RST65,RST55,INTR,RESETTRAP,RESETRST75,RESET,CK,SIM: in bit;
    BUSIN: in bit_vector(0 to 4);
	ID19,ID14,ID12,ID3,M1,T4,T2,INTACK,VCC: in bit
    );
end;

architecture structure of intrupt1 is

component prioenco
port( A : out bit_vector(2 downto 0);
      I0,I1,I2,I3,I4,EN : in bit);
end component;

signal L1, L2, L3, L4, L5, L6, L7, L8, L9, L10: bit;
signal EIBAR, RST75SET_BUF: bit;
signal n0, n1, n2, n3, n4, n5, n6, n7, n8, n9: bit;
signal n10, n11, n12, n14, n15, n17, n18 : bit;
signal n20, n21, n22 : bit;

begin
U0 : nor_gate generic map(1,1) port map(n0,M1,T2);
U1 : and_gate generic map(1,1) port map(n1,SIM,n0);
U2 : and_gate generic map(1,1) port map(n2,BUSIN(3),CK,n1);
U3 : DFF1 port map(L1,BUSIN(2),n2,RESET,VCC);
U4 : DFF1 port map(L3,BUSIN(1),n2,RESET,VCC);
U5 : DFF1 port map(L5,BUSIN(0),n2,RESET,VCC);
U3a : inv_gate port map(L2,L1);
U4a : inv_gate port map(L4,L3);
U5a : inv_gate port map(L6,L5);
U6 : and_gate generic map(1,1) port map(n6,RESET,RESETTRAP);
U7 : DFF1 port map(L7,VCC,TRAP,VCC,n6);
U8 : nand_gate generic map(1,1) port map(n8,n3,RST75SET_BUF);
U9 : nand_gate generic map(1,1) port map(n9,n4,RST65);
U10 : nand_gate generic map(1,1) port map(n10,n5,RST55);
U11 : nand_gate generic map(1,1) port map(n11,TRAP,n7);
U12 : inv_gate generic map(1,1) port map(n12,INTR);
U13 : DFF1 port map(L8,VCC,RST75,VCC,n14);
U14 : and_gate generic map(1,1) port map(n14,RESETRST75,RESET,n15);
U15 : nand_gate generic map(1,1) port map(n15,BUSIN(4),n1);
U16 : prioenco port map(PRIENCODE(2 downto 0),n11,n8,n9,n10 ,n12,EIBAR);
U17 : nor_gate generic map(1,1) port map(n17,T4,ID14,n22);
U18 : and_gate generic map(1,1) port map(n18,n17,CK);
U19 : DFF1 port map(L9,VCC,n18,VCC,n20);
U19a : inv_gate port map(L10,L9);
U20 : and_gate generic map(1,1) port map(n20,RESET,INTACK,n21);
U21 : or_gate generic map(1,1) port map(n21,T4,ID12,n22);
U22 : or_gate generic map(1,1) port map(n22,ID19,ID3);

U30 : buf_gate generic map (2,2) port map(MASK75SET,L1);
U31 : buf_gate generic map (2,2) port map(n3,L2);
U32 : buf_gate generic map (2,2) port map(MASK65SET,L3);
U33 : buf_gate generic map (2,2) port map(n4,L4);
U34 : buf_gate generic map (2,2) port map(MASK55SET,L5);
U35 : buf_gate generic map (2,2) port map(n5,L6);
U36 : buf_gate generic map (2,2) port map(n7,L7);
U37 : buf_gate generic map (2,2) port map(RST75SET_BUF,L8);
u37a : buf_gate port map(RST75SET,RST75SET_BUF);
U38 : buf_gate generic map (2,2) port map(EI,L9);
U39 : buf_gate generic map (2,2) port map(EIBAR,L10);
end structure;

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