Design Analyzer (TM)
DC Professional (TM)
DC Expert (TM)
FPGA Compiler (TM)
VHDL Compiler (TM)
HDL Compiler (TM)
Library Compiler (TM)
Test Compiler (TM)
Version v3.1a -- Mar 16, 1994
Copyright (c) 1988-1994 by Synopsys, Inc.
ALL RIGHTS RESERVED
design_analyzer> read -format vhdl {"/tmp_mnt/users/tech8/hendrich/vhdl/drink/drink.vhd"}
Loading db file '/local/tech15/synopsys/libraries/syn/standard.sldb'
Loading db file '/local/tech15/synopsys/libraries/syn/gtech.db'
Loading vhdl file '/tmp_mnt/users/tech8/hendrich/vhdl/drink/drink.vhd'
Reading in the Synopsys vhdl primitives.
/tmp_mnt/users/tech8/hendrich/vhdl/drink/drink.vhd:
Inferred memory devices in process 'reg_p'
in routine drink line 116 in file
'/tmp_mnt/users/tech8/hendrich/vhdl/drink/drink.vhd'.
===============================================================================
| Register Name | Type | Width | Bus | AR | AS | SR | SS | ST |
===============================================================================
| current_state_reg | Flip-flop | 3 | Y | Y | N | N | N | N |
===============================================================================
Current design is now '/tmp_mnt/users/tech8/hendrich/vhdl/drink/drink.db:drink'
{"drink"}
design_analyzer> create_schematic -size infinite -gen_database
Loading db file '/local/tech15/synopsys/libraries/syn/generic.sdb'
Loading db file '/local/tech15/synopsys/libraries/view.sdb'
Loading db file '/local/tech15/synopsys/libraries/StdLib_cdk.sdb'
Loading db file '/local/tech15/synopsys/libraries/OscLib_cdk.sdb'
Loading db file '/local/tech15/synopsys/libraries/PadLib_cdk.sdb'
Loading db file '/local/tech15/synopsys/libraries/basic_cdk.sdb'
Loading db file '/local/tech15/synopsys/libraries/sheets_cdk.sdb'
Loading db file '/local/tech15/synopsys/libraries/syn/1_25.font'
1
design_analyzer> Loading db file '/local/tech15/synopsys/libraries/ecpd10_ind.db'
create_schematic -size infinite -symbol_view
Warning: Design 'drink' isn't mapped. (UIS-3)
1
design_analyzer> create_schematic -size infinite -hier_view
Warning: Design 'drink' isn't mapped. (UIS-3)
1
design_analyzer> compile -map_effort medium
Loading target library 'ecpd10_ind'
Loading design 'drink'
Information: Design 'drink' has no optimization constraints set. (OPT-108)
Beginning CMOS optimization
---------------------------
Beginning Resource Allocation (area only)
-----------------------------
Allocating blocks in 'drink'
Allocating blocks in 'drink'
Information: Read implementation 'str' for synthetic design 'DW01_MUX'
from design library 'DW01'. (SYNH-2)
Allocating blocks in 'DW01_MUX'
Structuring 'DW01_MUX'
Mapping 'DW01_MUX'
Information: Modeled DW01_MUX(str).
(Wire load = -default- Operating Conditions = -default-) (SYNH-3)
Information: Read implementation 'str' for synthetic design 'DW01_mmux_2'
from design library 'DW01'. (SYNH-2)
Allocating blocks in 'DW01_mmux_2'
Structuring 'DW01_mmux_2'
Mapping 'DW01_mmux_2'
Information: Modeled DW01_mmux_2(str).
(Wire load = -default- Operating Conditions = -default-) (SYNH-3)
Information: Read implementation 'str' for synthetic design 'DW01_mmux_3'
from design library 'DW01'. (SYNH-2)
Allocating blocks in 'DW01_mmux_3'
Structuring 'DW01_mmux_3'
Mapping 'DW01_mmux_3'
Information: Modeled DW01_mmux_3(str).
(Wire load = -default- Operating Conditions = -default-) (SYNH-3)
Information: Read implementation 'str' for synthetic design 'DW01_mmux_4'
from design library 'DW01'. (SYNH-2)
Allocating blocks in 'DW01_mmux_4'
Structuring 'DW01_mmux_4'
Mapping 'DW01_mmux_4'
Information: Modeled DW01_mmux_4(str).
(Wire load = -default- Operating Conditions = -default-) (SYNH-3)
Information: Read implementation 'str' for synthetic design 'DW01_mmux_5'
from design library 'DW01'. (SYNH-2)
Allocating blocks in 'DW01_mmux_5'
Structuring 'DW01_mmux_5'
Mapping 'DW01_mmux_5'
Information: Modeled DW01_mmux_5(str).
(Wire load = -default- Operating Conditions = -default-) (SYNH-3)
Information: Read implementation 'str' for synthetic design 'DW01_NAND2'
from design library 'DW01'. (SYNH-2)
Allocating blocks in 'DW01_NAND2'
Structuring 'DW01_NAND2'
Mapping 'DW01_NAND2'
Information: Modeled DW01_NAND2(str).
(Wire load = -default- Operating Conditions = -default-) (SYNH-3)
Information: Read implementation 'str' for synthetic design 'DW01_NOT'
from design library 'DW01'. (SYNH-2)
Allocating blocks in 'DW01_NOT'
Structuring 'DW01_NOT'
Mapping 'DW01_NOT'
Information: Modeled DW01_NOT(str).
(Wire load = -default- Operating Conditions = -default-) (SYNH-3)
Beginning Mapping Optimizations (Medium effort)
-------------------------------
Structuring 'drink'
Mapping 'drink'
Information: Changed wire load model for 'drink' from '(none)' to '209X209'. (OPT-170)
OPTIMIZATION DESIGN RULE
TRIALS AREA DELTA DELAY COST COST
-------- ------ ----------- ------ ------
0
--------
0
Optimization complete
---------------------
Transferring Design 'drink' to database 'drink.db'
Current design is 'drink'.
1
design_analyzer> current_design = "/tmp_mnt/users/tech8/hendrich/vhdl/drink/drink.db:drink"
Current design is 'drink'.
"/tmp_mnt/users/tech8/hendrich/vhdl/drink/drink.db:drink"
design_analyzer> create_schematic -size infinite -gen_database
1
design_analyzer> create_schematic -size infinite -schematic_view -symbol_view -hier_view
Generating schematic for design: drink
The schematic for design 'drink' has 1 page(s).
1
design_analyzer> read -format vhdl {"/tmp_mnt/users/tech8/hendrich/vhdl/drink/drink.vhd"}
Loading vhdl file '/tmp_mnt/users/tech8/hendrich/vhdl/drink/drink.vhd'
/tmp_mnt/users/tech8/hendrich/vhdl/drink/drink.vhd:
Inferred memory devices in process 'reg_p'
in routine drink line 116 in file
'/tmp_mnt/users/tech8/hendrich/vhdl/drink/drink.vhd'.
===============================================================================
| Register Name | Type | Width | Bus | AR | AS | SR | SS | ST |
===============================================================================
| current_state_reg | Flip-flop | 3 | Y | Y | N | N | N | N |
===============================================================================
Warning: Overwriting design file '/tmp_mnt/users/tech8/hendrich/vhdl/drink/drink.db'. (DDB-24)
Current design is now '/tmp_mnt/users/tech8/hendrich/vhdl/drink/drink.db:drink'
{"drink"}
design_analyzer> create_schematic -size infinite -gen_database
1
design_analyzer> create_schematic -size infinite -symbol_view
Warning: Design 'drink' isn't mapped. (UIS-3)
1
design_analyzer> create_schematic -size infinite -hier_view
Warning: Design 'drink' isn't mapped. (UIS-3)
1
design_analyzer> compile -map_effort medium
Loading design 'drink'
Information: Design 'drink' has no optimization constraints set. (OPT-108)
Beginning CMOS optimization
---------------------------
Beginning Resource Allocation (area only)
-----------------------------
Allocating blocks in 'drink'
Allocating blocks in 'drink'
Beginning Mapping Optimizations (Medium effort)
-------------------------------
Structuring 'drink'
Mapping 'drink'
Information: Changed wire load model for 'drink' from '(none)' to '209X209'. (OPT-170)
OPTIMIZATION DESIGN RULE
TRIALS AREA DELTA DELAY COST COST
-------- ------ ----------- ------ ------
0
--------
0
Optimization complete
---------------------
Transferring Design 'drink' to database 'drink.db'
Current design is 'drink'.
1
design_analyzer> current_design = "/tmp_mnt/users/tech8/hendrich/vhdl/drink/drink.db:drink"
Current design is 'drink'.
"/tmp_mnt/users/tech8/hendrich/vhdl/drink/drink.db:drink"
design_analyzer> create_schematic -size infinite -gen_database
1
design_analyzer> create_schematic -size infinite -schematic_view -symbol_view -hier_view
Generating schematic for design: drink
The schematic for design 'drink' has 1 page(s).
1
design_analyzer>
Thank you...
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