entity reg4 is
end reg4;



architecture struct of reg4 is
  
  signal d0, d1, d2, d3, q0, q1, q2, q3, en, clk : bit;
  signal int_clk : bit;

begin -- behav
  
  gate : int_clk <= en and clk after 1 ns;

  D_ffs : block (int_clk ='1')
  begin
  
    bit0 : q0 <= guarded d0 after 1 ns;

    bit1 : q1 <= guarded d1 after 1 ns;

    bit2 : q2 <= guarded d2 after 1 ns;

    bit3 : q3 <= guarded d3 after 1 ns;

  end block;

  test : process
  begin

    d0 <= '1' after 10 ns;
    d1 <= '1' after 10 ns;
    d2 <= '1' after 10 ns;
    d3 <= '1' after 10 ns;
    en <= '1' after 10 ns;
    clk <= '1' after 15 ns, '0' after 25 ns;
    wait for 100 ns;
    
    d0 <= '0' after 10 ns;
    d1 <= '0' after 10 ns;
    d2 <= '0' after 10 ns;
    d3 <= '0' after 10 ns;
    en <= '1' after 10 ns;
    clk <= '1' after 15 ns, '0' after 25 ns;
    wait for 100 ns;
    
    d0 <= '1' after 10 ns, '0' after 25 ns;
    d1 <= '1' after 10 ns, '0' after 25 ns;
    d2 <= '1' after 10 ns, '0' after 25 ns;
    d3 <= '1' after 10 ns, '0' after 25 ns;
    en <= '0' after 10 ns, '1' after 20 ns;
    clk <= '1' after 15 ns, '0' after 30 ns;
    wait for 100 ns;
    
    wait;

  end process test;

end struct;