entity reg4 is
end reg4;



architecture behav of reg4 is
  
  signal d0, d1, d2, d3, q0, q1, q2, q3, en, clk : bit;

begin -- behav
  
  reg : process (d0, d1, d2, d3, en, clk)
    variable stored_d0, stored_d1, stored_d2, stored_d3 : bit;
  begin 
    if en = '1' and clk = '1' then
      stored_d0 := d0;
      stored_d1 := d1;
      stored_d2 := d2;
      stored_d3 := d3;
    end if;
    q0 <= stored_d0 after 2 ns;
    q1 <= stored_d1 after 2 ns;
    q2 <= stored_d2 after 2 ns;
    q3 <= stored_d3 after 2 ns;
  end process reg;

  test : process
  begin

    d0 <= '1' after 10 ns;
    d1 <= '1' after 10 ns;
    d2 <= '1' after 10 ns;
    d3 <= '1' after 10 ns;
    en <= '1' after 10 ns;
    clk <= '1' after 15 ns, '0' after 25 ns;
    wait for 100 ns;
    
    d0 <= '0' after 10 ns;
    d1 <= '0' after 10 ns;
    d2 <= '0' after 10 ns;
    d3 <= '0' after 10 ns;
    en <= '1' after 10 ns;
    clk <= '1' after 15 ns, '0' after 25 ns;
    wait for 100 ns;
    
    d0 <= '1' after 10 ns, '0' after 25 ns;
    d1 <= '1' after 10 ns, '0' after 25 ns;
    d2 <= '1' after 10 ns, '0' after 25 ns;
    d3 <= '1' after 10 ns, '0' after 25 ns;
    en <= '0' after 10 ns, '1' after 20 ns;
    clk <= '1' after 15 ns, '0' after 30 ns;
    wait for 100 ns;
    
    wait;

  end process test;

end behav;