Mentor QHDL Environment Setup

This page documents the steps used in creating a directory structure compatible with the Mentor QHDL environment in the Unix environment. For the Win95/WinNT environment, see Win95/WinNT setup .

Grab the file vhdl_course.zip and unzip via: directory, do the following:

 
  unzip vhdl_course.zip

This will setup a directory structure that looks like:

  vhdl_course/src/
	         /Makefiles    -- Makefiles for VHDL libraries
	         /exam1        -- source directory for VHDL example #1 
	        /utilities     -- various files that define useful
	                       -- VHDL packages which we will use in
                               -- this course
  vhdl_course/obj/qhdl/
	              /exam1        -- compiled VHDL object code for example #1
		      /utilities    -- compiled VHDL object code for utilities

Except for the 'Makefiles' directory, each directory under the 'src' directory represents a VHDL 'library'. The VHDL files within the library contain VHDL entities, packages, and configurations that reside within the library. Under the 'Makefiles' directory, there is a 'Makefile' for each VHDL library, i.e:

     src/Makefiles/Makefile.exam1    - makefile for library 'exam1'
     src/Makefiles/Makefile.utilities    - makefile for library 'utilities'

Compiling using a Makefile

To compile the contents of a library using one of the Makefiles, change directories to the 'src' directory and do:

      swsetup mgc
      gmake -f Makefiles/Makefile.exam1  TOOLSET=qhdl

This will compile the contents of the 'exam1' library. The Makefile has been written to be compatible with several VHDL simulators, hence the use of the 'TOOLSET' variable. The 'swsetup' command only has to be issued once in order to put the Mentor QHDL tools on your path; you may want to add this to your .cshrc file.

ECE Machines

If you are running this software from one of the ECE machines, you will need to be on a machine which is running Solaris and not Sun OS4. One easy way to determine if the machine has been converted to Solaris is to do :

   % which xmail

If this command returns a path for the 'mailx' program, then it is probably running Solaris. All of the workstations in the 1st floor Simrall workstation room have been converted to Solaris.

On ECE machines, the default 'make' is GNU make. There is no 'gmake' on ECE machines.

peavey:reese> which make
/opt/gnu/bin/make

Adding new VHDL entities/packages/configurations to a library

If you want to add new VHDL entities/packages/configurations to an existing library then:

Create the files in the target library directory (i.e., src/exam1/myfile.vhd).
Create the update rules for the file in the Makefile (i.e., src/Makefiles/Makefile.exam1).

When editing the Makefile, look at how the update rules for the other VHDL files are done and simply follow the same pattern.

Adding a new library

If you want to add your own VHDL library, then follow these steps, all of which must be executed from within the 'src/' directory:

Create the new library directory
```
	mkdir mylib
```
Create the QHDL library object directory via:
```
     qhlib ../obj/qhdl/mylib
     mkdir ../obj/qhdl/mylib/ts
```
The result of this command will be a new directory '../obj/qhdl/mylib' which will have some QHDL setup files in it. The 'ts' directory holds timestamp information required by our Makefile setup.
Create a logical to physical name mapping for the new library via:
```
     qhmap  mylib ../obj/qhdl/mylib
  
```
This command edits the 'src/quickhdl.ini' file and adds a logical to physical name mapping entry.
Create a 'Makefiles/Makefile.mylib' makefile that will handle the compilation of any VHDL files in 'mylib'. You can copy one of the other library Makefiles and edit it.

Running the 'exam1' VHDL code

The 'src/exam1' directory contains the following files:

dlatch.vhd - VHDL entity of simple D latch
tb.vhd - VHDL entity of a test bench which instantiates two latches, a stim component, and a trace component.
stim.vhd - VHDL entity of a stimulus module for the testbench
trace.vhd - VHDL entity of a trace module for the testbench
tb_cfg.vhd - VHDL configuration for the testbench which specifies the architectures and GENERIC values of each component.

The 'stim.vhd' entity applies test vectors to the test bench; the last test vector is applied at 151 ns. The following command will run the simulation in batch mode for a 160 ns:

  qhsim -c -lib ../obj/qhdl/exam1 cfg_tb  -do "run 160 ns;quit"

The '-c' option specifies that 'qhsim' should be run in batch mode. The -lib option specifies the library, in this case '../obj/qhdl/exam1'. The next parameter, 'cfg_tb', must be the name of the VHDL entity OR configuration to be executed. The '-do' option specifes the commands to be executed; these commands can either be directly specified as shown or contained in a file.

The 'qhsim' simulator can also be run in an interactive mode which is useful for debugging. Do this via:

  qhsim -lib ../obj/qhdl/exam1 cfg_tb  &

You should see a bunch of 'loading' messages as VHDL object code modules are loaded. From within this window, type:

 view *

This will cause MANY windows to pop up; do not be intimidated by the number of windows. The windows and their functions are as follows:

source - displays the VHDL source of the current process
variables - displays the values of the variables of the currently active process
signals - displays the signal values of the currently selected process
wave - waveform display window
structure - shows the VHDL component heirarchy of your model
dataflow - shows the inputs/outputs of the current process
process - shows the current the process 'stack' listing
list - a listing window which you can use to log variable/signal variables.

The most useful windows will be the 'source', 'variables', 'signals', and 'wave' windows; you can terminate the rest of the windows by clicking right on their top edge and selecting 'quit' from the pop-up menu.

The 'wave' window is used to display signal waveforms during simulation execution. I have prepared a command file to add signals to this window; the file is called 'wave.do' and is in the 'src/' directory. To execute this command file, type:

 do wave.do

in the main simulation window. Click on the 'wave' window and see what signals got added. These are signals which are defined in the 'tb.vhd' file which is the top-level entity.

To run the simulation for 160 ns, type:

 run 160 ns

The signals in the wave window will be updated as shown:

Restart versus Loading Changed Code

If you want to restart the simulation from time 0, then execute the 'File->Restart design' command as shown below.

If you edit a VHDL file and recompile, you can execute the 'File->Load new design' command to load in the changed code. This is faster than quitting the simulator and starting it up again.

Breakpoints

You can set a breakpoint in an entity by using the 'Structure' window to locate the component; click on the target component and then the 'Source' window will show the VHDL source for that component. To set a breakpoint, click on the VHDL line in the source line for the breakpoint and a red dot will appear. To remove the breakpoint, click on the VHDL line again. Use the 'Step' and 'Step Over' buttons in the VHDL simulation to single step the simulation. The 'Structure' and 'Source' window are shown below:

Win95/NT V-System Environment Setup

You can run this software on your homePC if desired. Requirements are a Pentium class machine, 16Mb of memory, and Win95/NT. You will given a V-system CD and a hardware 'key' that plugs into the parallel printer port of the PC. The hardware key will act as a pass thru to the printer. However, do NOT use this key with a bidirectional device like a tape drive. You will need to write a $200 check payable to MSU as a deposit for the key; the check will be returned at the end of the semester when you return the key.

Install Vsystem by placing the CD in the drive, then execute the 'setup' program on the CD under Vsystem/disk1 directory. Follow the setup instructions. This should install on your 'start' menu a "ModelTech -> Vsystem" entry.

Unpack the 'vhdl_course.zip' file somewhere on your system. DELETE everything under the "vhdl_course/obj/qhdl" directory.

Creating Libraries

Startup Vsystem via the ModelTech->Vsystem choice on the startmenu.

In the V-system window, use the "File->Directory" command to change to the "vhdl_course\obj\qhdl" directory.

Use the Library->New command to create a library - name it 'utilities'. This should create a directory called 'vhdl_course\obj\qhdl\utilities". Next, use the "Library->Mapping' command to bring up the library mapping window. Use the 'New' command to create a library to directory mapping for the 'utilities' library. The library name should be 'utilities', the directory name should be the FULL PATHNAME to this library, i.e (C:\vhdl_course\obj\qhdl\utilities). This will create an entry in your "C:\vsystem\vsystem.ini" file that looks like:

 utilities = C:\vhdl_course\obj\qhdl\utilities

You could also edit the "C:\vsystem\vsystem.ini" file directly to set this mapping.

Library creation and library name mapping only has to be done ONCE!

Compiling Files

The Makefiles used on the Unix side are incompatible with Win95/NT so compilation has to be done 'manually' through the Vsystem interface.

Now use the File->Directory command to change to the vhdl_course\src\utilities directory (you can also use the 'cd' command from the 'V-system' prompt to change directories, the 'pwd' command be used to print the current directory).

Use the File->Compile VHDL command to bring up the VHDL compile window. Edit the 'Target Library' (will be currently 'work') and change it to 'utilities'. You can now click on a VHDL file, then hit the 'compile' command to compile a VHDL file. Before doing this, use the "Options" button and make sure that the 'Optimize for 1164-standard' and 'Use 1076-1993 language standard' options are checked.

The 'utilities' directory contain some VHDL packages that we will use. Each package consists of a package body and a package header (filename ends in a '_' for the package header). Compile the package header first, then the body. You should compile the 'standard_utils' package, then the 'std_logic_1164_utils' package. There is NO need to compile the memory, mem_page_small, or jedec_reader packages (these packages will not compile with the 1076-1993 option checked, you have to uncheck this option for these packages if you wish to compile them).

Follow the same sequence of steps to create an 'exam1' library, the 'obj/qhdl/exam1' to directory mapping, and then compile the 'src/exam1' files. When compiling the "src/exam1" files, you will need to compile them in this order:

 dlatch (entity and architecture in one file)
 stim entity
 stim architectures
 trace entity (entity and architecture in one file)
 tb
 configurations

The reason for this ordering is dependencies - configurations depend on the tb (test bench) which depend on the components used in the testbench, etc...

If the VHDL entity/architecture is split between two files, then when compiling files, you have to compile the file that contains the entity first, then compile the file that specifies the architecture.

Compiling Files

To run the simulation, change to the 'vhdl_course/src' directory, and from the "V-system>" command line, type:

  vsim -lib exam1

You will be prompted with a window that shows the various configurations and entities in the 'exam1' library. Choose 'cfg_tb'. You should see the 'V-system' prompt change to 'VSIM' and the various debugging windows appear in closed form at the bottom of the screen. Open the 'wave' window, and type 'do wave.do' at the VSIM command prompt to get the signals to appear in the wave window. Type 'run 150 ns' to run the simulation for 150 ns. Type 'quit' to exit the simulator; the prompt should change back to 'V-system'.