"A 177 Mb/s VLSI Implementation of the International Data Encryption Algorithm"

R. Zimmermann, A. Curiger, H. Bonnenberg, 
H. Kaeslin, N. Felber, and W. Fichtner

Abstract
--------

A VLSI implementation of the International Data Encryption Algorithm is
presented. Security considerations led to novel system concepts in chip design
including protection of sensitive information and on-line failure detection
capabilities. BIST was instrumental for reconciling contradicting requirements
of VLSI testability and cryptographic security. The VLSI chip implements data
encryption and decryption in a single hardware unit. All important
standardized modes of operation of block ciphers, such as ECB, CBC, CFB, OFB
and MAC, are supported. In addition, new modes are proposed and implemented to
fully exploit the algorithm's inherent parallelism. With a system clock
frequency of 25 MHz the device permits a data conversion rate of more than 177
Mbit/s. Therefore, the chip can be applied to on-line encryption in high-speed
networking protocols like ATM or FDDI.