Peter Ashenden
Department of Computer Science, University of Adelaide, Australia
February 1999
This project involves extending the SUAVE/SAVANT compiler to generate control/data flow graphs (CDFGs). GDFGs represent the flow of sequential control and operands between operators in a VHDL model, and are used as the basis for synthesis of hardware from a behavioural description of a system. No hardware design background is assumed.
This project will start with the "scram" analyzer for standard VHDL. Scram forms part of the SAVANT tool suite under development at the University of Cincinnati. Scram uses freely available compiler-generator tools (flex and PCCTS) to build a parser. Actions routines in the grammar file generate an extensible intermediate form using the AIRE abstract syntax classes. Tree-processing methods perform static semantic analysis and generate C++ code to be compiled and linked with the TyVIS distributed simulation kernel. The SUAVE Project is currently extending the SAVANT tools to implement the SUAVE language extensions.
The CDFG Generator project will involve adding new functionality to the scram analyzer to traverse the abstract syntax tree and generate CDFGs for models expressed in standard VHDL and in the SUAVE superset. The project will also involve development of a suite of tools for manipulating CDFGs, allowing for transformations that optimize control and data flow. If time permits, some basic optimizations may be implemented. Examples of optimizations include common-subexpression elimination, loop unrolling, and other optimizations that are often seen in compilers for programming languages.
Peter Ashenden
Dept. Computer Science, University of Adelaide, SA 5005, Australia
Phone: +61 8 8303 4477
Fax: +61 8 8303 4366
Email: petera@cs.adelaide.edu.au